View PSD4235G2-90U_2008680.PDF datasheet online --- IC-ON-LINE

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1/100 march 2004 psd4235g2 flash in-system programmable (isp) for 16-bit mcus (5v supply) features summary dual bank flash memories ? 4 mbit of primary flash memory (8 uniform sectors, 32k x 16) ? 256 kbit secondary flash memory with 4 sectors ? concurrent operation: read from one memory while erasing and writing the other 64 kbit sram (battery backed) pld with macrocells ? over 3000 gates of pld: cpld and dpld ? cpld with 16 output macrocells (omcs) and 24 input macrocells (imcs) ? dpld - user defined internal chip select decoding seven l/o ports with 52 i/o pins ? 52 individually configurable i/o port pins that can be used for the following functions: ? mcu i/os ?pld i/os ? latched mcu address output ? special function l/os ? l/o ports may be configured as open-drain outputs in-system programming (isp) with jtag ? built-in jtag compliant serial port allows full-chip in-system programmability ? efficient manufacturing allow easy product testing and programming ? use low cost flashlink cable with pc page register ? internal page register that can be used to expand the microcontroller address space by a factor of 256 programmable power management figure 1. package high endurance: ? 100,000 erase/write cycles of flash memory ? 1,000 erase/write cycles of pld ? 15 year data retention single supply voltage ? 5v 10% memory speed ? 70ns flash memory and sram access time tqfp80 (u) 80-lead, thin, quad, flat
psd4235g2 2/100 table of contents features summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 figure 1. package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 in-system programming (isp) via jtag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 first time programming.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 inventory build-up of pre-programmed devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 expensive sockets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 in-application programming (iap). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 simultaneous read and write to flash memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 complex memory mapping.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 separate program and data space. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 psdsoft express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 2. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 1. pin names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 3. tqfp connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 2. pin description (for the tqfp package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 4. psd block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 psd architectural overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 plds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 i/o ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 mcu bus interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 isp via jtag port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 3. pld i/o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 4. jtag signals on port e. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 in-system programming (isp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 in-application programming (iap). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 page register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 power management unit (pmu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 7 table 5. methods of programming different functional blocks of the psd . . . . . . . . . . . . . . . . . 17 development system. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 5. psdsoft express development tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 psd register description and address offsets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 6. register address offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 register bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 7. data-in registers - ports a, b, c, d, e, f, g. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3/100 psd4235g2 table 8. data-out registers - ports a, b, c, d, e, f, g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 9. direction registers - ports a, b, c, d, e, f, g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 10. control registers - ports e, f, g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 11. drive registers - ports a, b, d, e, g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 12. drive registers - ports c, f. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 13. enable-out registers - ports a, b, c, f . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 14. input macrocells - ports a, b, c. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 table 15. output macrocells a register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 16. output macrocells b register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 17. mask macrocells a register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 18. mask macrocells b register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 19. flash memory protection register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 20. flash boot protection register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 21. jtag enable register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 22. page register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 23. pmmr0 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 24. pmmr2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 25. vm register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 26. memory_id0 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 27. memory_id1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 detailed operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 memory blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 28. memory block size and organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 primary flash memory and secondary flash memory description . . . . . . . . . . . . . . . . . . . . . 26 memory block select signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 ready/busy (pe4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 memory operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 29. instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 power-up condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 reading flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 read memory contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 read primary flash identifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 read memory sector protection status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 reading the erase/program status bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 30. status bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 31. status bits for motorola . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 data polling (dq7) - dq15 for motorola . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 toggle flag (dq6) - dq14 for motorola . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 error flag (dq5) - dq13 for motorola . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 0 erase time-out flag (dq3) - dq11 for motorola. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 programming flash memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 data polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
psd4235g2 4/100 figure 6. data polling flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 data toggle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 unlock bypass. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 7. data toggle flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 erasing flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 flash bulk erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 flash sector erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 suspend sector erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 resume sector erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 specific features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 flash memory sector protect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 reset (r eset ) pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 sram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 memory select signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 memory select configuration for mcus with separate program and data spaces . . . . . . . . 35 figure 8. priority level of memory and i/o components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 separate space modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 combined space modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 80c51xa memory map example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 9. 8031 memory modules - separate space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 10.8031 memory modules - combined space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 page register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 11.page register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 memory id registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 plds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 the turbo bit in psd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 32. dpld and cpld inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 figure 12.pld diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 decode pld (dpld). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 13.dpld logic array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 complex pld (cpld) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 14.macrocell and i/o port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 output macrocell (omc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 33. output macrocell port and data bit assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 product term allocator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
5/100 psd4235g2 loading and reading the output macrocells (omc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 the omc mask register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 the output enable of the omc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 figure 15.cpld output macrocell. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 input macrocells (imc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 16.input macrocell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 external chip select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 17.external chip select signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 18.handshaking communication using input macrocells . . . . . . . . . . . . . . . . . . . . . . . . . . 46 mcu bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 34. mcus and their control signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 psd interface to a multiplexed bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 19.an example of a typical 16-bit multiplexed bus interface . . . . . . . . . . . . . . . . . . . . . . . 48 psd interface to a non-multiplexed 8-bit bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 20.an example of a typical 16-bit non-multiplexed bus interface . . . . . . . . . . . . . . . . . . . 49 data byte enable reference. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 35. 16-bit data bus with bhe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 mcu bus interface examples. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 table 36. 16-bit data bus with wrh and wrl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 37. 16-bit data bus with siz0, a0 (motorola mcu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 38. 16-bit data bus with lds, uds (motorola mcu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 80c196 and 80c186 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 21.interfacing the psd with an 80c196 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 mc683xx and mc68hc16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 22.interfacing the psd with an mc68331 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 80c51xa . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 23.interfacing the psd with an 80c51xa-g3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 h8/300 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 24.interfacing the psd with an h83/2350 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 mmc2001 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 c16x family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 25.interfacing the psd with an mmc2001 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 figure 26.interfacing the psd with a c167cr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 i/o ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 general port architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 port operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 27.general i/o port architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 mcu i/o mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 pld i/o mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 address out mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 39. port operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 40. port operating mode settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1 table 41. i/o port latched address output assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 address in mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
psd4235g2 6/100 data port mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 peripheral i/o mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 figure 28.peripheral i/o mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 jtag in-system programming (isp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 mcu reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 port configuration registers (pcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 42. port configuration registers (pcr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 direction register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 drive select register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 43. port pin direction control, output enable p.t. not defined . . . . . . . . . . . . . . . . . . . . . . 64 table 44. port pin direction control, output enable p.t. defined . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 45. port direction assignment example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 46. drive register pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4 port data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 data in. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 data out register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 output macrocells (omc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 mask macrocell register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 input macrocells (imc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 47. port data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 enable out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 ports a, b and c - functionality and structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 figure 29.port a, b and c structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 port d - functionality and structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 figure 30.port d structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 port e - functionality and structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 port f - functionality and structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 port g - functionality and structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 figure 31.port e, f and g structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 automatic power-down (apd) unit and power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 power-down mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 48. effect of power-down mode on ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 figure 32.apd unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 49. psd timing and stand-by current during power-down mode . . . . . . . . . . . . . . . . . . . . 71 other power saving options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 pld power management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 sram stand-by mode (battery backup) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 psd chip select input (csi, pd2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 input clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 figure 33.enable power-down flow chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 input control signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 table 50. apd counter operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
7/100 psd4235g2 power-on reset, warm reset and power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 warm reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 i/o pin, register and pld status at reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 reset of flash memory erase and program cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 51. status during power-on reset, warm reset and power-down mode . . . . . . . . . . . . . . 74 figure 34.reset (reset) timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 programming in-circuit using the jtag serial interface . . . . . . . . . . . . . . . . . . . . . . 75 standard jtag signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 jtag extensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 security and flash memory protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 table 52. jtag port signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 initial delivery state. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 ac/dc parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 figure 35.pld icc /frequency consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 table 53. example of psd typical power calculation at v cc = 5.0v (with turbo mode on) . . . . . 78 table 54. example of psd typical power calculation at v cc = 5.0v (with turbo mode off) . . . . . 79 maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 table 55. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 0 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 table 56. operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 table 57. ac signal letters for pld timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 table 58. ac signal behavior symbols for pld timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 table 59. ac measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 table 60. capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 figure 36.ac measurement i/o waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 figure 37.ac measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 figure 38.switching waveforms - key . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 table 61. dc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 figure 39.input to output disable / enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 table 62. cpld combinatorial timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4 table 63. cpld macrocell synchronous clock mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 table 64. cpld macrocell asynchronous clock mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 figure 40.synchronous clock mode timing - pld . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 figure 41.asynchronous r eset / preset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 figure 42.asynchronous clock mode timing (product term clock) . . . . . . . . . . . . . . . . . . . . . . . . . 86 figure 43.input macrocell timing (product term clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 table 65. input macrocell timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 table 66. program, write and erase times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 figure 44.peripheral i/o write timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
psd4235g2 8/100 figure 45.read timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 table 67. read timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 figure 46.write timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 table 68. write timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 figure 47.peripheral i/o read timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 table 69. port f peripheral data mode read timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 table 70. port f peripheral data mode write timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 figure 48.reset (reset ) timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 table 71. reset (reset )timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 table 72. power-down timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 table 73. v stbyon timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 figure 49.isc timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 table 74. isc timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 figure 50.tqfp80 - 80-lead plastic thin, quad, flat package outline . . . . . . . . . . . . . . . . . . . . . 95 table 75. tqfp80 - 80-lead plastic thin, quad, flat package mechanical data. . . . . . . . . . . . . . 96 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 table 76. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 7 appendix a.pin assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 table 77. psd4235g2 tqfp80 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 table 78. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
9/100 psd4235g2 summary description the psd family of memory systems for microcon- trollers (mcus) brings in-system-programmability (isp) to flash memory and programmable logic. the result is a simple and flexible solution for em- bedded designs. psd devices combine many of the peripheral functions found in mcu based ap- plications. psd devices integrate an optimized macrocell log- ic architecture. the macrocell was created to ad- dress the unique requirements of embedded system designs. it allows direct connection be- tween the system address/data bus, and the inter- nal psd registers, to simplify communication between the mcu and other supporting devices. the psd family offers two methods to program the psd flash memory while the psd is soldered to the circuit board: in-system programming (isp) via jtag an ieee 1149.1 compliant jtag in-system pro- gramming (isp) interface is included on the psd enabling the entire device (flash memories, pld, configuration) to be rapidly programmed while sol- dered to the circuit board. this requires no mcu participation, which means the psd can be pro- grammed anytime, even when completely blank. the innovative jtag interface to flash memories is an industry first, solving key problems faced by designers and manufacturing houses, such as: first time programming. how do i get firmware into the flash memory the very first time? jtag is the answer. program the blank psd with no mcu involvement. inventory build-up of pre-programmed devic- es. how do i maintain an accurate count of pre- programmed flash memory and pld devices based on customer demand? how many and what version? jtag is the answer. build your hardware with blank psds soldered directly to the board and then custom program just before they are shipped to the customer. no more labels on chips, and no more wasted inventory. expensive sockets. how do i eliminate the need for expensive and unreliable sockets? jtag is the answer. solder the psd directly to the circuit board. program first time and subsequent times with jtag. no need to handle devices and bend the fragile leads. in-application programming (iap) two independent flash memory arrays are includ- ed so that the mcu can execute code from one while erasing and programming the other. robust product firmware updates in the filed are possible over any communication channel (can, ethernet, uart, j1850, etc) using this unique architecture. designers are relieved of these problems: simultaneous read and write to flash mem- ory. how can the mcu program the same memo- ry from which it executing code? it cannot. the psd allows the mcu to operate the two flash memory blocks concurrently, reading code from one while erasing and programming the other dur- ing iap. complex memory mapping. how can i map these two memories efficiently? a programmable decode pld (dpld) is embedded in the psd. the concurrent psd memories can be mapped anywhere in mcu address space, segment by segment with extermely high address resolution. as an option, the secondary flash memory can be swapped out of t he system memory map when iap is complete. a built-in page register breaks the mcu address limit. separate program and data space. how can i write to flash memory while it resides in program space during field firmware updates? my 80c51xa will not allow it. the psd provides means to reclassify flash memory as data space during iap, then back to program space when complete. psdsoft express psdsoft express, a software development tool from st, guides you through the design process step-by-step making it possible to complete an embedded mcu design capable of isp/iap in just hours. select your mcu and psdsoft express takes you through the remainder of the design with point and click entry, covering psd selection, pin definitions, programmable logic inputs and outpus, mcu memory map definition, ansi-c code gener- ation for your mcu, and merging your mcu firm- ware with the psd design. when complete, two different device programmers are supported di- rectly from psdsoft express: flashlink (jtag) and psdpro.
psd4235g2 10/100 figure 2. logic diagram table 1. pin names ai04916 16 ad0-ad15 pf0-pf7 v cc psd4xxxgx v ss 8 pg0-pg7 8 pb0-pb7 8 pa0-pa7 8 3 cntl0- cntl2 reset pd0-pd3 4 pc0-pc7 8 pe0-pe7 8 pa0-pa7 port-a pb0-pb7 port-b pc0-pc7 port-c pd0-pd3 port-d pe0-pe7 port-e pf0-pf7 port-f pg0-pg7 port-g ad0-ad15 address/data cntl0-cntl2 control reset reset v cc supply voltage v ss ground
11/100 psd4235g2 figure 3. tqfp connections 60 cntl1 59 cntl0 58 pa7 57 pa6 56 pa5 55 pa4 54 pa3 53 pa2 52 pa1 51 pa0 50 gnd 49 gnd 48 pc7 47 pc6 46 pc5 45 pc4 44 pc3 43 pc2 42 pc1 41 pc0 pd2 pd3 ad0 ad1 ad2 ad3 ad4 gnd v cc ad5 ad6 ad7 ad8 ad9 ad10 ad11 ad12 ad13 ad14 ad15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 pd1 pd0 pe7 pe6 pe5 pe4 pe3 pe2 pe1 pe0 gnd v cc pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 pg0 pg1 pg2 pg3 pg4 pg5 pg6 pg7 v cc gnd pf0 pf1 pf2 pf3 pf4 pf5 pf6 pf7 reset cntl2 ai04943
psd4235g2 12/100 pin description table 2. pin description (for the tqfp package) pin name pin type description adio0- adio7 3-7 10-12 i/o this is the lower address/data port. connect your mcu address or address/data bus according to the following rules: 1. if your mcu has a multiplexed address/data bus where the data is multiplexed with the lower address bits, connect ad0-ad7 to this port. 2. if your mcu does not have a multiplexed address/data bus, connect a0-a7 to this port. 3. if you are using an 80c51xa in burst mode, connect a4/d0 through a11/d7 to this port. ale or as latches the address. the psd drives data out only if the read signal is active and one of the psd functional blocks has been selected. the addresses on this port are passed to the plds. adio8- adio15 13-20 i/o this is the upper address/data port. connect your mcu address or address/data bus according to the following rules: 1. if your mcu has a multiplexed address/data bus where the data is multiplexed with the upper address bits, connect a8-a15 to this port. 2. if your mcu does not have a multiplexed address/data bus, connect a8-a15 to this port. 3. if you are using an 80c51xa in burst mode, connect a12/d8 through a19/d15 to this port. ale or as latches the address. the psd drives data out only if the read signal is active and one of the psd functional blocks has been selected. the addresses on this port are passed to the plds. cntl0 59 i the following control signals can be connected to this pin, based on your mcu: 1. wr - active low, write strobe input. 2. r_w - active high, read/active low write input. 3. wrl - active low, write to low-byte. this pin is connected to the plds. therefore, these signals can be used in decode and other logic equations. cntl1 60 i the following control signals can be connected to this pin, based on your mcu: 1. rd - active low, read strobe input. 2. e - e clock input. 3. ds - active low, data strobe input. 4. lds - active low, strobe for low data byte. this pin is connected to the plds. therefore, these signals can be used in decode and other logic equations. cntl2 40 i read or other control input pin, with multiple configurations. depending on the mcu interface selected, this pin can be: 1. psen - program select enable, active low in code fetch bus cycle (80c51xa mode). 2. bhe - high-byte enable, 16-bit data bus. 3. uds - active low, strobe for high data byte, 16-bit data bus mode. 4. siz0 - byte enable input. 5. lstrb - low strobe input. this pin is also connected to the plds. reset 39 i active low input. resets i/o ports, pld macrocells and some of the configuration registers and jtag registers. must be low at power-up. reset also aborts any flash memory program or erase cycle that is currently in progress. pa0-pa7 51-58 i/o cmos or open drain these pins make up port a. these port pins are configurable and can have the following functions: 1. mcu i/o - standard output or input port. 2. cpld macrocell (mcella0-mcella7) outputs. 3. latched, transparent or registered pld inputs (can also be pld input for address a16 and above).
13/100 psd4235g2 pb0-pb7 61-68 i/o cmos or open drain these pins make up port b. these port pins are configurable and can have the following functions: 1. mcu i/o - standard output or input port. 2. cpld macrocell (mcellb0-mcellb7) outputs. 3. latched, transparent or registered pld inputs (can also be pld input for address a16 and above). pc0-pc7 41-48 i/o cmos or slew rate these pins make up port c. these port pins are configurable and can have the following functions: 1. mcu i/o - standard output or input port. 2. external chip select (ecs0-ecs7) outputs. 3. latched, transparent or registered pld inputs (can also be pld input for address a16 and above). pd0 79 i/o cmos or open drain pd0 pin of port d. this port pin can be configured to have the following functions: 1. ale/as input - latches address on adio0-adio15. 2. as input - latches address on adio0-adio15 on the rising edge. 3. mcu i/o - standard output or input port. 4. transparent pld input (can also be pld input for address a16 and above). pd1 80 i/o cmos or open drain pd1 pin of port d. this port pin can be configured to have the following functions: 1. mcu i/o - standard output or input port. 2. transparent pld input (can also be pld input for address a16 and above). 3. clkin - clock input to the cpld macrocells, the apd unit?s power-down counter, and the cpld and array. pd2 1 i/o cmos or open drain pd2 pin of port d. this port pin can be configured to have the following functions: 1. mcu i/o - standard output or input port. 2. transparent pld input (can also be pld input for address a16 and above). 3. psd chip select input (csi ). when low, the mcu can access the psd memory and i/o. when high, the psd memory blocks are disabled to conserve power. the falling edge of this signal can be used to get the device out of power-down mode. pd3 2 i/o cmos or open drain pd3 pin of port d. this port pin can be configured to have the following functions: 1. mcu i/o - standard output or input port. 2. transparent pld input (can also be pld input for address a16 and above). 3. wrh - for 16-bit data bus, write to high byte, active low. pe0 71 i/o cmos or open drain pe0 pin of port e. this port pin can be configured to have the following functions: 1. mcu i/o - standard output or input port. 2. latched address output. 3. tms input for the jtag serial interface. pe1 72 i/o cmos or open drain pe1 pin of port e. this port pin can be configured to have the following functions: 1. mcu i/o - standard output or input port. 2. latched address output. 3. tck input for the jtag serial interface. pe2 73 i/o cmos or open drain pe2 pin of port e. this port pin can be configured to have the following functions: 1. mcu i/o - standard output or input port. 2. latched address output. 3. tdi input for the jtag serial interface. pe3 74 i/o cmos or open drain pe3 pin of port e. this port pin can be configured to have the following functions: 1. mcu i/o - standard output or input port. 2. latched address output. 3. tdo output for the jtag serial interface. pin name pin type description
psd4235g2 14/100 pe4 75 i/o cmos or open drain pe4 pin of port e. this port pin can be configured to have the following functions: 1. mcu i/o - standard output or input port. 2. latched address output. 3. tstat output for the jtag serial interface. 4. ready/busy output for parallel in-system programming (isp). pe5 76 i/o cmos or open drain pe5 pin of port e. this port pin can be configured to have the following functions: 1. mcu i/o - standard output or input port. 2. latched address output. 3. terr active low output for the jtag serial interface. pe6 77 i/o cmos or open drain pe6 pin of port e. this port pin can be configured to have the following functions: 1. mcu i/o - standard output or input port. 2. latched address output. 3. v stby - sram stand-by voltage input for sram battery backup. pe7 78 i/o cmos or open drain pe7 pin of port e. this port pin can be configured to have the following functions: 1. mcu i/o - standard output or input port. 2. latched address output. 3. battery-on indicator (vbaton). goes high when power is being drawn from the external battery. pf0-pf7 31-38 i/o cmos or open drain these pins make up port f. these port pins are configurable and can have the following functions: 1. mcu i/o - standard output or input port. 2. external chip select (ecs0-ecs7) outputs, or inputs to cpld. 3. latched address outputs. 4. address a1-a3 inputs in 80c51xa mode (pf0 is grounded) 5. data bus port (d0-d7) in a non-multiplexed bus configuration. 6. peripheral i/o mode. 7. mcu reset mode. pg0-pg7 21-28 i/o cmos or open drain these pins make up port g. these port pins are configurable and can have the following functions: 1. mcu i/o - standard output or input port. 2. latched address outputs. 3. data bus port (d8-d15) in a non-multiplexed bus configuration. 4. mcu reset mode. v cc 9, 29, 69 supply voltage gnd 8, 30, 49, 50, 70 ground pins pin name pin type description
15/100 psd4235g2 figure 4. psd block diagram note: additional address lines can be brought in to the device via port a, b, c, d or f. prog. mcu bus intrf. adio port cntl0, cntl1, cntl2 ad0 ? ad15 clkin clkin clkin pld input bus prog. port port a prog. port port b power mangmt unit 4 mbit primary flash memory 16 sectors vstdby pa0 ? pa7 pb0 ? pb7 prog. port port c prog. port port d pc0 ? pc7 pd0 ? pd3 address/data/control bus port a & b 8 ext cs to port c or f 24 input macrocells port a ,b & c 82 82 256 kbit secondary flash memory (boot or data) 4 sectors 64 kbit battery backup sram runtime control and i/o registers sram select perip i/o mode selects macrocell feedback or port input csiop flash isp cpld (cpld) 16 output macrocells flash decode pld ( dpld ) pld, configuration & flash memory loader jtag serial channel ( pe6 ) page register embedded algorithm sector selects sector selects global config. & security ai04990 8 prog. port port e pe0 ? pe7 port f prog. port port f pf0 ? pf7 prog. port port g pg0 ? pg7
psd4235g2 16/100 psd architectural overview psd devices contain several major functional blocks. figure 4 shows the architecture of the psd device family. the functions of each block are de- scribed briefly in the following sections. many of the blocks perform multiple functions and are user configurable. memory each of the memory blocks is briefly discussed in the following paragraphs. a more detailed discus- sion can be found in the section entitled ?memory blocks? on page 25. the 4 mbit primary flash memory is the main memory of the psd. it is divided into 8 equally- sized sectors that are individually selectable. the 256 kbit secondary flash memory is divided into 4 equally-sized sectors. each sector is individ- ually selectable. the 64 kbit sram is intended for use as a scratch-pad memory or as an extension to the mcu sram. if an external battery is connected to the psd?s voltage stand-by (v stby , pe6) signal, data is retained in the event of power failure. each memory block can be located in a different address space as defined by the user. the access times for all memory types includes the address latching and dpld decoding time. plds the device contains two pld blocks, the decode pld (dpld) and the complex pld (cpld), as shown in table 3, each optimized for a different function. the functional partitioning of the plds reduces power consumption, optimizes cost/per- formance, and eases design entry. the dpld is used to decode addresses and to generate sector select signals for the psd inter- nal memory and registers. the dpld has combi- natorial outputs, while the cpld can implement more general user-defined logic functions. the cpld has 16 output macrocells (omc) and 8 combinatorial outputs. the psd also has 24 input macrocells (imc) that can be configured as inputs to the plds. the plds receive their inputs from the pld input bus and are differentiated by their output destinations, number of product terms, and macrocells. the plds consume minimal power. the speed and power consumption of the pld is controlled by the turbo bit in pmmr0 and other bits in pmmr2. these registers are set by the mcu at run-time. there is a slight penalty to pld propaga- tion time when not in the turbo mode. i/o ports the psd has 52 i/o pins divided among seven ports (port a, b, c, d, e, f and g). each i/o pin can be individually configured for different func- tions. ports can be configured as standard mcu i/ o ports, pld i/o, or latched address outputs for mcus using multiplexed address/data buses the jtag pins can be enabled on port e for in- system programming (isp). mcu bus interface the psd easily interfaces easily with most 16-bit mcus, either with multiplexed or non-multiplexed address/data buses. the device is configured to respond to the mcu?s control pins, which are also used as inputs to the plds. isp via jtag port in-system programming (isp) can be performed through the jtag signals on port e. this serial in- terface allows complete programming of the entire psd device. a blank device can be completely programmed. the jtag signals (tms, tck, tstat, terr , tdi, tdo) can be multiplexed with other functions on port e. table 4 indicates the jtag pin assignments. table 3. pld i/o table 4. jtag signals on port e name inputs outputs product terms decode pld (dpld) 82 17 43 complex pld (cpld) 82 24 150 port e pins jtag signal pe0 tms pe1 tck pe2 tdi pe3 tdo pe4 tstat pe5 terr
17/100 psd4235g2 in-system programming (isp) using the jtag signals on port e, the entire psd device (memory, logic, configuration) can be pro- grammed or erased without the use of the mcu. in-application programming (iap) the primary flash memory can also be pro- grammed, or re-programmed, in-system by the mcu executing the programming algorithms out of the secondary flash memory, or sram. the sec- ondary flash memory can be programmed the same way by executing out of the primary flash memory. table 5 indicates which programming methods can program different functional blocks of the psd. page register the 8-bit page register expands the address range of the mcu by up to 256 times. the paged address can be used as part of the address space to access external memory and peripherals, or in- ternal memory and i/o. the page register can also be used to change the address mapping of the flash memory blocks into different memory spaces for iap. power management unit (pmu) the power management unit (pmu) gives the user control of the power consumption on selected functional blocks based on system requirements. the pmu includes an automatic power-down (apd) unit that turns off device functions during mcu inactivity. the apd unit has a power-down mode that helps reduce power consumption. the psd also has some bits that are configured at run-time by the mcu to reduce power consump- tion of the cpld. the turbo bit in pmmr0 can be reset to ?0? and the cpld latches its outputs and goes to stand-by mode until the next transition on its inputs. additionally, bits in pmmr2 can be set by the mcu to block signals from entering the cpld to reduce power consumption. see the section enti- tled ?power management? on page 70 for more de- tails. table 5. methods of programming different functional blocks of the psd functional block jtag-isp device programmer iap primary flash memory yes yes yes secondary flash memory yes yes yes pld array (dpld and cpld) yes yes no psd configuration yes yes no
psd4235g2 18/100 development system the psd family is supported by psdsoft express, a windows-based software development tool (windows-95, windows-98, windows-2000, win- dows-nt). a psd design is quickly and easily pro- duced in a point and click environment. the designer does not need to enter hardware de- scription language (hdl) equations, unless de- sired, to define psd pin functions and memory map information. the general design flow is shown in figure 5. psdsoft express is available from our web site (the address is given on the back page of this data sheet) or other distribution chan- nels. psdsoft express directly supports two low cost device programmers form st: psdpro and flashlink (jtag). both of these programmers may be purchased through your local distributor/ representative, or directly from our web site using a credit card. the psd is also supported by thid party device programmers. see our web site for the current list. figure 5. psdsoft express development tool merge mcu firmware with psd configuration psd programmer *.obj file psdpro, or flashlink (jtag) a composite object file is created containing mcu firmware and psd configuration c code generation generate c code specific to psd functions user's choice of microcontroller compiler/linker *.obj file available for 3rd party programmers (conventional or jtag-isc) mcu firmware hex or s-record format ai04919 define general purpose logic in cpld point and click definition of combin- atorial and registered logic in cpld. access hdl is available if needed define psd pin and node functions point and click definition of psd pin functions, internal nodes, and mcu system memory map choose mcu and psd automatically configures mcu bus interface and other psd attributes
19/100 psd4235g2 psd register description and address offsets table 6 shows the offset addresses to the psd registers relative to the csiop base address. the csiop space is the 256 bytes of address that is al- located by the user to the internal psd registers. table 6 provides brief descriptions of the registers in csiop space. the following sections give a more detailed description. table 6. register address offset note: 1. other registers that are not part of the i/o ports. register name port a port b port c port d port e port f port g other (1) description data in 00 01 10 11 30 40 41 reads port pin as input, mcu i/o input mode control 32 42 43 selects mode between mcu i/o or address out data out 04 05 14 15 34 44 45 stores data for output to port pins, mcu i/o output mode direction 06 07 16 17 36 46 47 configures port pin as input or output drive select 08 09 18 19 38 48 49 configures port pins as either cmos or open drain on some pins, while selecting high slew rate on other pins. input macrocell 0a 0b 1a reads input macrocells enable out 0c 0d 1c 4c reads the status of the output enable to the i/o port driver output macrocells a 20 read - reads output of macrocells a write - loads macrocell flip-flops output macrocells b 21 read - reads output of macrocells b write - loads macrocell flip-flops mask macrocells a 22 blocks writing to the output macrocells a mask macrocells b 23 blocks writing to the output macrocells b flash memory protection c0 read only - primary flash sector protection flash boot protection c2 read only - psd security and secondary flash memory sector protection jtag enable c7 enables jtag port pmmr0 b0 power management register 0 pmmr2 b4 power management register 2 page e0 page register vm e2 places psd memory areas in program and/or data space on an individual basis. memory_id0 f0 read only - sram and primary memory size memory_id1 f1 read only - secondary memory type and size
psd4235g2 20/100 register bit definition all the registers of the psd are included here, for reference. detailed descriptions of these registers can be found in the following sections. table 7. data-in registers - ports a, b, c, d, e, f, g note: bit definitions (read-only registers): read port pin status when port is in mcu i/o input mode. table 8. data-out registers - ports a, b, c, d, e, f, g note: bit definitions: latched data for output to port pin when pin is configured in mcu i/o output mode. table 9. direction registers - ports a, b, c, d, e, f, g note: bit definitions: port pin 0 = port pin is configured in input mode (default). port pin 1 = port pin is configured in output mode. table 10. control registers - ports e, f, g note: bit definitions: port pin 0 = port pin is configured in mcu i/o mode (default). port pin 1 = port pin is configured in latched address out mode. table 11. drive registers - ports a, b, d, e, g note: bit definitions: port pin 0 = port pin is configured for cmos output driver (default). port pin 1 = port pin is configured for open drain output driver. table 12. drive registers - ports c, f note: bit definitions: port pin 0 = port pin is configured for cmos output driver (default). port pin 1 = port pin is configured in slew rate mode. bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 port pin 7 port pin 6 port pin 5 port pin 4 port pin 3 port pin 2 port pin 1 port pin 0 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 port pin 7 port pin 6 port pin 5 port pin 4 port pin 3 port pin 2 port pin 1 port pin 0 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 port pin 7 port pin 6 port pin 5 port pin 4 port pin 3 port pin 2 port pin 1 port pin 0 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 port pin 7 port pin 6 port pin 5 port pin 4 port pin 3 port pin 2 port pin 1 port pin 0 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 port pin 7 port pin 6 port pin 5 port pin 4 port pin 3 port pin 2 port pin 1 port pin 0 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 port pin 7 port pin 6 port pin 5 port pin 4 port pin 3 port pin 2 port pin 1 port pin 0
21/100 psd4235g2 table 13. enable-out registers - ports a, b, c, f note: bit definitions (read-only registers): port pin 0 = port pin is in tri-state driver (default). port pin 1 = port pin is enabled. table 14. input macrocells - ports a, b, c note: bit definitions (read-only registers): read input macrocell (imc7-imc0) status on ports a, b and c. table 15. output macrocells a register note: bit definitions: write register: load mcella7-mcella0 with 0 or 1. read register: read mcella7-mcella0 output status. table 16. output macrocells b register note: bit definitions: write register: load mcellb7-mcellb0 with 0 or 1. read register: read mcellb7-mcellb0 output status. table 17. mask macrocells a register note: bit definitions: mcella_prot 0 = allow mcella flip-flop to be loaded by mcu (default). mcella_prot 1 = prevent mcella flip-flop from being loaded by mcu. table 18. mask macrocells b register note: bit definitions: mcellb_prot 0 = allow mcellb flip-flop to be loaded by mcu (default). mcellb_prot 1 = prevent mcellb flip-flop from being loaded by mcu. table 19. flash memory protection register note: bit definitions (read-only register): sec_prot 1 = primary flash memory sector is write protected. sec_prot 0 = primary flash memory sector is not write protected. bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 port pin 7 port pin 6 port pin 5 port pin 4 port pin 3 port pin 2 port pin 1 port pin 0 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 imcell 7 imcell 6 imcell 5 imcell 4 imcell 3 imcell 2 imcell 1 imcell 0 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 mcella 7 mcella 6 mcella 5 mcella 4 mcella 3 mcella 2 mcella 1 mcella 0 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 mcellb 7 mcellb 6 mcellb 5 mcellb 4 mcellb 3 mcellb 2 mcellb 1 mcellb 0 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 mcella 7 mcella 6 mcella 5 mcella 4 mcella 3 mcella 2 mcella 1 mcella 0 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 mcellb 7 mcellb 6 mcellb 5 mcellb 4 mcellb 3 mcellb 2 mcellb 1 mcellb 0 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 sec7_prot sec6_prot sec5_prot sec4_prot sec3_prot sec2_prot sec1_prot sec0_prot
psd4235g2 22/100 table 20. flash boot protection register note: bit definitions: sec_prot 1 = secondary flash memory sector is write protected. sec_prot 0 = secondary flash memory sector is not write protected. security_bit 0 = security bit in device has not been set. security_bit 1 = security bit in device has been set. table 21. jtag enable register note: bit definitions: jtagenable 1 = jtag port is enabled. jtagenable 0 = jtag port is disabled. table 22. page register note: bit definitions: configure page input to pld. default is pgr7-pgr0=0. bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 security_bit not used not used not used sec3_prot sec2_prot sec1_prot sec0_prot bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 not used not used not used not used not used not used not used jtagenable bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 pgr 7pgr 6pgr 5pgr 4pgr 3pgr 2pgr 1pgr 0
23/100 psd4235g2 table 23. pmmr0 register note: the bits of this register are cleared to zero following power-up. subsequent reset (reset ) pulses do not clear the registers. note: bit definitions: apd enable 0 = automatic power-down (apd) is disabled. 1 = automatic power-down (apd) is enabled. pld turbo 0 = pld turbo is on. 1 = pld turbo is off, saving power. pld array clk 0 = clkin to the pld and array is connected. every clkin change powers up the pld when turbo bit is off. 1 = clkin to the pld and array is disconnected, saving power. pld mcells clk 0 = clkin to the pld macrocells is connected. 1 = clkin to the pld macrocells is disconnected, saving power. table 24. pmmr2 register note: for bit 4, bit 3, bit 2: see table 34 for the signals that are blocked on pins cntl0-cntl2. note: bit definitions: pld array addr 0 = address a7-a0 are connected to the pld array. 1 = address a7-a0 are blocked from the pld array, saving power. (note: in xa mode, a3-a0 come from pf3-pf0, and a7-a4 come from adio7-adio4) pld array cntl2 0 = cntl2 input to the pld and array is connected. 1 = cntl2 input to the pld and array is disconnected, saving power. pld array cntl1 0 = cntl1 input to the pld and array is connected. 1 = cntl1 input to the pld and array is disconnected, saving power. pld array cntl0 0 = cntl0 input to the pld and array is connected. 1 = cntl0 input to the pld and array is disconnected, saving power. pld array ale 0 = ale input to the pld and array is connected. 1 = ale input to the pld and array is disconnected, saving power. pld array wrh 0 = wrh/dbe input to the pld and array is connected. 1 = wrh/dbe input to the pld and array is disconnected, saving power. table 25. vm register note: on reset, bit1-bit4 are loaded to configurations that are selected by the user in psdsoft express. bit0 and bit7 are alway s cleared on reset. bit0-bit4 are active only when the device is configured in philips 80c51xa mode. note: bit definitions: sr_code 0 = psen cannot access sram in 80c51xa modes. 1 = psen can access sram in 80c51xa modes. boot_code 0 = psen cannot access secondary nvm in 80c51xa modes. 1 = psen can access secondary nvm in 80c51xa modes. fl_code 0 = psen cannot access primary flash memory in 80c51xa modes. 1 = psen can access primary flash memory in 80c51xa modes. boot_data 0 = rd cannot access secondary nvm in 80c51xa modes. 1 = rd can access secondary nvm in 80c51xa modes. fl_data 0 = rd cannot access primary flash memory in 80c51xa modes. 1 = rd can access primary flash memory in 80c51xa modes. peripheral mode 0 = peripheral mode of port f is disabled. 1 = peripheral mode of port f is enabled. bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 not used (set to ?0?) not used (set to ?0?) pld mcells clk pld array clk pld turbo not used (set to ?0?) apd enable not used (set to ?0?) bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 not used (set to ?0?) pld array wrh pld array ale pld array cntl2 pld array cntl1 pld array cntl0 not used (set to ?0?) pld array addr bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 peripheral mode not used (set to ?0?) not used (set to ?0?) fl_data boot_data fl_code boot_code sr_code
psd4235g2 24/100 table 26. memory_id0 register note: bit definitions: f_size[3:0] 0h = there is no primary flash memory 1h = primary flash memory size is 256 kbit 2h = primary flash memory size is 512 kbit 3h = primary flash memory size is 1 mbit 4h = primary flash memory size is 2 mbit 5h = primary flash memory size is 4 mbit 6 h = primary flash memory size is 8 mbit s_size[3:0] 0h = there is no sram 1h = sram size is 16 kbit 2h = sram size is 32 kbit 3 h = sram size is 64 kbit 4h = sram size is 128 kbit 5 h = sram size is 256 kbit table 27. memory_id1 register note: bit definitions: b_size[3:0] 0h = there is no secondary nvm 1 h = secondary nvm size is 128 kbit 2h = secondary nvm size is 256 kbit 3 h = secondary nvm size is 512 kbit b_type[1:0] 0h = secondary nvm is flash memory 1h = secondary nvm is eeprom bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 s_size 3 s_size 2 s_size 1 s_size 0 f_size 3 f_size 2 f_size 1 f_size 0 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 not used (set to ?0?) not used (set to ?0?) b_type 1 b_type 0 b_size 3 b_size 2 b_size 1 b_size 0
25/100 psd4235g2 detailed operation as shown in figure 4, the psd consists of six ma- jor types of functional blocks: memory blocks pld blocks mcu bus interface i/o ports power management unit (pmu) jtag-isp interface the functions of each block are described in the following sections. many of the blocks perform multiple functions, and are user configurable. memory blocks the psd has the following memory blocks: ? primary flash memory ? secondary flash memory ?sram the memory select signals for these blocks origi- nate from the decode pld (dpld) and are user- defined in psdsoft express. table 28 sumamarizes the sizes and organisa- tions of the memory blocks. table 28. memory block size and organization primary flash memory secondary flash memory sram sector number sector size (x16) sector select signal sector size (x16) sector select signal sram size (x16) sram select signal 0 32k fs0 4k csboot0 4k rs0 1 32k fs1 4k csboot1 2 32k fs2 4k csboot2 3 32k fs3 4k csboot3 4 32k fs4 5 32k fs5 6 32k fs6 7 32k fs7 totals 512kbyte 8 sectors 32kbyte 4 sectors 8kbyte
psd4235g2 26/100 primary flash memory and secondary flash memory description the primary flash memory is divided evenly into 8 sectors. the secondary flash memory is divided evenly into 4 sectors. each sector of either memo- ry block can be separately protected from program and erase cycles. flash memory may be erased on a sector-by-sec- tor basis, and programmed word-by-word. flash sector erasure may be suspended while data is read from other sectors of the block and then re- sumed after reading. during a program or erase cycle in flash memory, the status can be output on the ready/busy pin (pe4). this pin is set up using psdsoft express. memory block select signals. the dpld gen- erates the select signals for all the internal memo- ry blocks (see the section entitled ?plds?, on page 38). each of the sectors of the primary flash mem- ory has a select signal (fs0-fs7) which can con- tain up to three product terms. each of the sectors of the secondary flash memory has a select sig- nal (csboot0-csboot3) which can contain up to three product terms. having three product terms for each select signal allows a given sector to be mapped in different ar eas of system memory. when using a mcu with separate program and data space (80c51xa), these flexible select sig- nals allow dynamic re-mapping of sectors from one memory space to the other before and after iap. the sram block has a single select signal (rs0). ready/busy (pe4). this signal can be used to output the ready/busy status of the psd. the out- put is a ?0? (busy) when a flash memory block is being written to, or when a flash memory block is being erased. the output is a ?1? (ready) when no write or erase cycle is in progress. memory operation the primary flash memory and secondary flash memory are addressed through the mcu bus in- terface. the mcu can access these memories in one of two ways: ? the mcu can execute a typical bus write or read operation just as it would if accessing a ram or rom device using standard bus cycles. ? the mcu can execute a specific instruction that consists of several write and read operations. this involves writing specific data patterns to special addresses within the flash memory to invoke an embedded algorithm. these instructions are summarized in table 29. typically, the mcu can read flash memory using read operations, just as it would read a rom de- vice. however, flash memory can only be erased and programmed using specific instructions. for example, the mcu cannot write a single byte di- rectly to flash memory as one would write a byte to ram. to program a word into flash memory, the mcu must execute a program instruction, then test the status of the programming event. this sta- tus test is achieved by a read operation or polling ready/busy (pe4). flash memory can also be read by using special instructions to retrieve particular flash device in- formation (sector protect status and id).
27/100 psd4235g2 table 29. instructions note: 1. all bus cycles are write bus cycles, except the ones with the ?read? label 2. all values are in hexadecimal: x = don?t care. addresses of the form xxxxh, in this table, must be even addresses ra = address of the memory location to be read rd = data read from location ra during the read cycle pa = address of the memory location to be programmed. addresses are latched on the falling edge of write strobe (wr , cntl0). pa is an even address for psd in word programming mode. pd = data word to be programmed at location pa. data is latched on the rising edge of write strobe (wr , cntl0) sa = address of the sector to be erased or verified. the sector select (fs0-fs7 or csboot0-csboot3) of the sector to be erased, or verified, must be active (high). 3. sector select (fs0 to fs7 or csboot0 to csboot3) signals are active high, and are defined in psdsoft express. 4. only address bits a11-a0 are used in instruction decoding. 5. no unlock or instruction cycles are required when the device is in the read mode 6. the reset instruction is required to return to the read mode after reading the flash id, or after reading the sector protecti on sta- tus, or if the error flag bit (dq5/dq13) goes high. 7. additional sectors to be erased must be written at the end of the sector erase instruction within 80s. 8. the data is 00h for an unprotected sector, and 01h for a protected sector. in the fourth cycle, the sector select is active, and (a1,a0)=(1,0) 9. the unlock bypass instruction is required prior to the unlock bypass program instruction. 10. the unlock bypass reset flash instruction is required to return to reading memory data when the device is in the unlock bypa ss mode. 11. the system may perform read and program cycles in non-erasing sectors, read the flash id or read the sector protection statu s when in the suspend sector erase mode. the suspend sector erase instruction is valid only during a sector erase cycle. 12. the resume sector erase instruction is valid only during the suspend sector erase mode. 13. the mcu cannot invoke these instructions while executing code from the same flash memory as that for which the instruction i s intended. the mcu must fetch, for example, the code from the secondary flash memory when reading the sector protection status of the primary flash memory. 14. all write bus cycles in an instruction are byte write to an even address (xa4ah or x554h). a flash memory program bus cycle writes a word to an even address. instruction 14 fs0-fs7 or csboot0- csboot3 cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 read 5 1 ?read? rd @ ra read main flash id 6 1 aah@ xaaah 55h@ x554h 90h@ xaaah read id @ xx02h read sector protection 6,8,13 1 aah@ xaaah 55h@ x554h 90h@ xaaah read 00h or 01h @ xx04h program a flash word 13 1 aah@ xaaah 55h@ x554h a0h@ xaaah pd@ pa flash sector erase 7,13 1 aah@ xaaah 55h@ x554h 80h@ xaaah aah@ xaaah 55h@ x554h 30h@ sa 30h 7 @ next sa flash bulk erase 13 1 aah@ xaaah 55h@ x554h 80h@ xaaah aah@ xaaah 55h@ x554h 10h@ xaaah suspend sector erase 11 1 b0h@ xxxxh resume sector erase 12 1 30h@ xxxxh reset 6 1 f0h@ xxxxh unlock bypass 1 aah@ xaaah 55h@ x554h 20h@ xaaah unlock bypass program 9 1 a0h@ xxxxh pd@ pa unlock bypass reset 10 1 90h@ xxxxh 00h@ xxxxh
psd4235g2 28/100 instructions an instruction consists of a sequence of specific operations. each received byte is sequentially de- coded by the psd and not executed as a standard write operation. the instruction is executed when the correct number of bytes are properly re- ceived and the time between two consecutive bytes is shorter than the time-out period. some in- structions are structured to include read opera- tions after the initial write operations. the instruction must be followed exactly. any in- valid combination of instruction bytes or time-out between two consecutive bytes while addressing flash memory resets the device logic into read mode (flash memory is read like a rom device). the psd supports the instructions summarized in table 29: erase memory by chip or sector suspend or resume sector erase program a word reset to read mode read primary flash identifier value read sector protection status bypass these instructions are detailed in table 29., page 27. for efficient decoding of the instructions, the first two bytes of an instruction are the coded cy- cles and are followed by an instruction byte or con- firmation byte. the coded cycles consist of writing the data aah to address xaaah during the first cy- cle and data 55h to address x554h during the sec- ond cycle (unless the bypass instruction feature is used, as described later). address signals a15- a12 are don?t care during the instruction write cycles. however, the appropriate sector select signal (fs0-fs7, or csboot0-csboot3) must be selected. the primary and secondary flash memories have the same instruction set (except for read primary flash identifier). the sector select signals deter- mine which flash memory is to receive and exe- cute the instruction. the primary flash memory is selected if any one of its sector select signals (fs0-fs7) is high, and the secondary flash mem- ory is selected if any one of its sector select sig- nals (csboot0-csboot3) is high. power-up condition the psd internal logic is reset upon power-up to the read mode. sector select (fs0-fs7 and csboot0-csboot3) must be held low, and write strobe (wr /wrl , cntl0) high, during power-up for maximum security of the data con- tents and to remove the possibility of data being written on the first edge of write strobe (wr /wrl , cntl0). any write cycle initiation is locked when v cc is below v lko . reading flash memory under typical conditions, the mcu may read the primary flash memory, or secondary flash mem- ory, using read operations just as it would a rom or ram device. alternately, the mcu may use read operations to obtain status information about a program or erase cycle that is currently in progress. lastly, the mcu may use instructions to read special data from t hese memory blocks. the following sections describe these read functions. read memory contents primary flash memory and secondary flash memory are placed in the read mode after pow- er-up, chip reset, or a reset flash instruction (see table 29). the mcu can read the memory con- tents of the primary flash memory, or the second- ary flash memory by using read operations any time the read operation is not part of an instruc- tion. read primary flash identifier the primary flash memory identifier is read with an instruction composed of 4 operations: 3 specific write operations and a read operation (see ta- ble 29). the identifier for the primary flash memo- ry is e8h. the secondary flash memory does not support this instruction. read memory sector protection status the flash memory sector protection status is read with an instruction composed of four opera- tions: three specific write operations and a read operation (see table 29). the read oper- ation produces 01h if the flash memory sector is protected, or 00h if the sector is not protected. the sector protection status for all nvm blocks (primary flash memory, or secondary flash mem- ory) can be read by the mcu accessing the flash protection and flash boot protection registers in psd i/o space. see the section entitled ?flash memory sector protect?, on page 34, for register definitions.
29/100 psd4235g2 reading the erase/program status bits the psd provides several status bits to be used by the mcu to confirm the completion of an erase or program cycle of flash memory. these status bits minimize the time that the mcu spends per- forming these tasks and are defined in table 30. the status byte resides in an even location, and can be read as many times as needed. also note that dq15-dq8 is an even byte for motorola mcus with a 16-bit data bus. for flash memory, the mcu can perform a read operation to obtain these status bits while an erase or program instruction is being executed by the embedded algorithm. see the section entitled ?programming flash memory?, on page 31, for details. table 30. status bits table 31. status bits for motorola note: 1. x = not guaranteed value, can be read either 1 or 0. 2. dq15-dq0 represent the data bus bits, d15-d0. 3. fs0-fs7/csboot0-csboot3 are active high. dq7 dq6 dq5 dq4 dq3 dq2 dq1 dq0 data polling toggle flag error flag x erase time- out xxx dq15 dq14 dq13 dq12 dq11 dq10 dq9 dq8 data polling toggle flag error flag x erase time- out xxx
psd4235g2 30/100 data polling (dq7) - dq15 for motorola when erasing or programming in flash memory, the data polling bit (dq7/dq15) outputs the com- plement of the bit being entered for programming/ writing on the dq7/dq15 bit. once the program instruction or the write operation is completed, the true logic value is read on the data polling bit (dq7/dq15, in a read operation). ? data polling is effective after the fourth write pulse (for a program instruction) or after the sixth write pulse (for an erase instruction). it must be performed at the address being programmed or at an address within the flash memory sector being erased. ? during an erase cycle, the data polling bit (dq7/dq15) outputs a '0.' after completion of the cycle, the data polling bit (dq7/dq15) outputs the last bit programmed (it is a ?1? after erasing). ? if the location to be programmed is in a protected flash memory sector, the instruction is ignored. ? if all the flash memory sectors to be erased are protected, the data polling bit (dq7/ dq15) is reset to ?0? for about 100s, and then returns to the value from the previously addressed location. no erasure is performed. toggle flag (dq6) - dq14 for motorola the psd offers another way for determining when the flash memory program cycle is completed. during the internal write operation and when ei- ther fs0-fs7 or csboot0-csboot3 is true, the toggle flag bit (dq6/dq14) bit toggles from 0 to ?1? and 1 to ?0? on subsequent attempts to read any word of the memory. when the internal cycle is complete, the toggling stops and the data read on the data bus d0-d7 is the value from the addressed memory location. the device is now accessible for a new read or write operation. the cycle is finished when two successive reads yield the same output data. ? the toggle flag bit (dq6/dq14) is effective after the fourth write pulse (for a program instruction) or after the sixth write pulse (for an erase instruction). ? if the location to be programmed belongs to a protected flash memory sector, the instruction is ignored. ? if all the flash memory sectors selected for erasure are protected, the toggle flag bit (dq6/dq14) toggles to ?0? for about 100s and then returns to the value from the previously addressed location. error flag (dq5) - dq13 for motorola during a normal program or erase cycle, the error flag bit (dq5/dq13) is reset to '0.' this bit is set to ?1? when there is a failure during a flash memory program, sector erase, or bulk erase cycle. in the case of flash memory programming, the er- ror flag bit (dq5/dq13) indicates the attempt to program a flash memory bit, or bits, from the pro- grammed state, 0, to the erased state, 1, which is not a valid operation. the error flag bit (dq5/ dq13) may also indicate a time-out condition while attempting to program a word. in case of an error in a flash memory sector erase or word program cycle, the flash memory sector in which the error occurred or to which the pro- grammed location belongs must no longer be used. other flash memory sectors may still be used. the error flag bit (dq5/dq13) is reset after a reset instruction. a reset instruction is required after detecting an error on the error flag bit (dq5/ dq13). erase time-out flag (dq3) - dq11 for motorola the erase time-out flag bit (dq3/dq11) reflects the time-out period allowed between two consecu- tive sector erase instructions. the erase time-out flag bit (dq3/dq11) is reset to ?0? after a sector erase cycle for a period of 100s + 20% unless an additional sector erase instruction is decoded. af- ter this period, or when the additional sector erase
31/100 psd4235g2 programming flash memory flash memory must be erased prior to being pro- grammed. the mcu may erase flash memory all at once or by-sector. although erasing flash mem- ory occurs on a sector or device basis, program- ming flash memory occurs on a word basis. the primary and secondary flash memories re- quire the mcu to send an instruction to program a word or to erase sectors (see table 29). once the mcu issues a flash memory program or erase instruction, it must check the status bits for completion. the embedded algorithms that are in- voked inside the psd support several means to provide status to the mcu. status may be checked using any of three methods: data polling, data toggle, or ready/busy (pe4) signal. data polling polling on the data polling bit (dq7/dq15) is a method of checking whether a program or erase cycle is in progress or has completed. figure 6 shows the data polling algorithm. when the mcu issues a program instruction, the embedded algorithm within the psd begins. the mcu then reads the location of the word to be pro- grammed in flash memory to check the status. the data polling bit (dq7/dq15) becomes the complement of the corresponding bit of the original data word to be programmed. the mcu continues to poll this location, comparing data and monitor- ing the error flag bit (dq5/dq13). when the data polling bit (dq7/dq15) matches the correspond- ing bit of the original data, and the error flag bit (dq5/dq13) remains 0, the embedded algorithm is complete. if the error flag bit (dq5/dq13) is 1, the mcu should test the data polling bit (dq7/ dq15) again since the da ta polling bit (dq7/ dq15) may have changed simultaneously with the error flag bit (dq5/dq13, see figure 6). the error flag bit (dq5/dq13) is set if either an internal time-out occurred while the embedded al- gorithm attempted to program the location or if the mcu attempted to program a ?1? to a bit that was not erased (not erased is logic 0). it is suggested (as with all flash memories) to read the location again after the embedded program- ming algorithm has completed, to compare the word that was written to the flash memory with the word that was intended to be written. when using the data polling method during an erase cycle, figure 6 still applies. however, the data polling bit (dq7/dq15) is 0 until the erase cycle is complete. a '1' on the error flag bit (dq5/ dq13) indicates a time-out condition on the erase cycle, a ?0? indicates no error. the mcu can read any even location within the sector being erased to get the data po lling bit(dq7/dq15) and the error flag bit (dq5/dq13). psdsoft express generates ansi c code func- tions that implement these data polling algo- rithms. figure 6. data polling flowchart read dq5 and dq7 (dq13 and dq15) at valid even address start read dq7 (dq15) program or erase cycle failed program or erase cycle is complete ai04920 yes no yes no dq5 (dq13) = 1 dq7 (dq15) = data7 (data15) yes no issue reset instruction dq7 (dq15) = data7 (data15)
psd4235g2 32/100 data toggle checking the toggle flag bit (dq6/dq14) is an- other method of determining whether a program or erase cycle is in progress or has completed. fig- ure 7 shows the data toggle algorithm. when the mcu issues a program instruction, the embedded algorithm within the psd begins. the mcu then reads the location to be programmed in flash memory to check the status. the toggle flag bit (dq6/dq14) toggles each time the mcu reads this location until the embedded algorithm is complete. the mcu continues to read this loca- tion, checking the toggle flag bit (dq6/dq14) and monitoring the error flag bit (dq5/dq13). when the toggle flag bit (dq6/dq14) stops tog- gling (two consecutive reads yield the same val- ue), and the error flag bit (dq5/dq13) remains 0, the embedded algorithm is complete. if the error flag bit (dq5/dq13) is 1, the mcu should test the toggle flag bit (dq6/dq14) again, since the tog- gle flag bit (dq6/dq14) may have changed si- multaneously with the error flag bit (dq5/dq13, see figure 7). the error flag bit (dq5/dq13) is set if either an internal time-out occurred while the embedded al- gorithm attempted to program, or if the mcu at- tempted to program a ?1? to a bit that was not erased (not erased is logic 0). it is suggested (as with all flash memories) to read the location again after the embedded program- ming algorithm has completed, to compare the word that was written to flash memory with the word that was intended to be written. when using the data toggle method after an erase cycle, figure 7 still applies. the toggle flag bit (dq6/dq14) toggles until the erase cycle is complete. a '1' on the error flag bit (dq5/dq13) indicates a time-out condition on the erase cycle, a ?0? indicates no error. the mcu can read any even location within the sector being erased to get the toggle flag bit (dq6/dq14) and the error flag bit (dq5/dq13). psdsoft express generates ansi c code func- tions which implement these data toggling algo- rithms. unlock bypass the unlock bypass instruction allows the system to program words to the flash memories faster than using the standard program instruction. the unlock bypass mode is entered by first initiating two unlock cycles. this is followed by a third write cycle containing the unlock bypass com- mand, 20h (as shown in table 29). the flash memory then enters the unlock bypass mode. a two-cycle unlock bypass program instruction is all that is required to program in this mode. the first cycle in this instruction contains the unlock bypass program command, a0h. the second cy- cle contains the program address and data. addi- tional data is programmed in the same manner. this mode dispense with the initial two unlock cy- cles required in the standard program instruction, resulting in faster total programming time. during the unlock bypass mode, only the unlock bypass program and unlock bypass reset in- structions are valid. to exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset instruc- tion. the first cycle must contain the data 90h; the second cycle the data 00h. addresses are don?t care for both cycles. the flash memory then re- turns to read mode. figure 7. data toggle flowchart start read dq6 (dq14) ai04921 no no yes yes no yes program or erase cycle failed program or erase cycle is complete issue reset instruction read dq5 and dq6 (dq13 and dq14) at valid even address dq5 (dq13) = 1 dq6 (dq14) = toggle dq6 (dq14) = toggle
33/100 psd4235g2 erasing flash memory flash bulk erase the flash bulk erase instruction uses six write operations followed by a read operation of the status register, as described in table 29. if any byte of the bulk erase instruction is wrong, the bulk erase instruction aborts and the device is re- set to the read memory mode. during a bulk erase, the memory status may be checked by reading the error flag bit (dq5/ dq13), the toggle flag bit (dq6/dq14), and the data polling bit (dq7/dq15), as detailed in the section entitled ?programming flash mem- ory?, on page 31. the error flag bit (dq5/dq13) returns a ?1? if there has been an erase failure (maximum number of erase cycles have been ex- ecuted). it is not necessary to program the memory with 00h because the psd automatically does this be- fore erasing to 0ffh. during execution of the bulk erase instruction, the flash memory does not accept any instructions. flash sector erase. the sector erase instruc- tion uses six write operations, as described in table 29. additional flash sector erase confirm commands and flash memory sector addresses can be written subsequently to erase other flash memory sectors in parallel, without further coded cycles, if the additional commands are transmitted in a shorter time than the time-out period of about 100s. the input of a new sector erase command restarts the time-out period. the status of the internal timer can be monitored through the level of the erase time-out flag bit (dq3/dq11). if the erase time-out flag bit (dq3/ dq11) is 0, the sector erase instruction has been received and the time-out period is counting. if the erase time-out flag bit (dq3/dq11) is 1, the time-out period has expired and the psd is busy erasing the flash memory sector(s). before and during erase time-out, any instruction other than suspend sector erase and resume sector erase, abort the cycle that is currently in progress, and re- set the device to read mode. it is not necessary to program the flash memory sector with 00h as the psd does this automatically before erasing. during a sector erase, the memory status may be checked by reading the error flag bit (dq5/ dq13), the toggle flag bit (dq6/dq14), and the data polling bit (dq7/dq15), as detailed in the section entitled ?programming flash mem- ory?, on page 31. during execution of the erase cycle, the flash memory accepts only reset and suspend sector erase instructions. erasure of one flash memory sector may be suspended, in order to read data from another flash memory sector, and then re- sumed. suspend sector erase when a sector erase cycle is in progress, the sus- pend sector erase instruction can be used to sus- pend the cycle by writi ng 0b0h to any even address when an appropriate sector select (fs0- fs7 or csboot0-csboot3) is high. (see table 29). this allows reading of data from another flash memory sector after the erase cycle has been suspended. suspend sector erase is ac- cepted only during the flash sector erase instruc- tion execution and defaults to read mode. a suspend sector erase instruction executed during an erase time-out period, in addition to suspend- ing the erase cycle, terminates the time out period. the toggle flag bit (dq6/dq14) stops toggling when the psd internal logic is suspended. the status of this bit must be monitored at an address within the flash memory sector being erased. the toggle flag bit (dq6/dq14) stops toggling be- tween 0.1s and 15s after the suspend sector erase instruction has been executed. the psd is then automatically set to read mode. if an suspend sector erase instruction was exe- cuted, the following rules apply: ? attempting to read from a flash memory sector that was being erased outputs invalid data. ? reading from a flash memory sector that was not being erased is valid. ? the flash memory cannot be programmed, and only responds to resume sector erase and reset instructions (read is an operation and is allowed). ? if a reset instruction is received, data in the flash memory sector that was being erased is invalid. resume sector erase if a suspend sector erase instruction was previ- ously executed, the erase cycle may be resumed with this instruction. the resume sector erase in- struction consists of writing 030h to any even ad- dress while an appropriate sector select (fs0- fs7 or csboot0-csboot3) is high. (see table 29.)
psd4235g2 34/100 specific features flash memory sector protect each sector of primary or secondary flash mem- ory can be separately protected against program and erase cycles. sector protection provides ad- ditional data security because it disables all pro- gram or erase cycles. this mode can be activated (or deactivated) through the jtag-isp port or a device programmer. sector protection can be selected for each sector using the psdsoft express program. this auto- matically protects selected sectors when the de- vice is programmed through the jtag port or a device programmer. flash memory sectors can be unprotected to allow updating of their contents using the jtag port or a device programmer. the mcu can read (but cannot change) the sector pro- tection bits. any attempt to program or erase a protected flash memory sector is ignored by the device. the verify operation results in a read of the protected data. this allows a guarantee of the retention of the pro- tection status. the sector protection status can be read by the mcu through the flash memory protection and secondary flash memory protection registers (in the csiop block) or use the read sector protec- tion instruction. see table 19 to table 20. reset the reset instruction consists of one write cy- cle (see table 29). it can also be optionally pre- ceded by the standard two write decoding cycles (writing aah to aaah, and 55h to 554h). the reset instruction must be executed after: ? reading the flash protection status or flash id ? an error condition has occurred (and the device has set the error flag bit (dq5/dq13) to ?1?) during a flash memory program or erase cycle. the reset instruction immediately puts the flash memory back into normal read mode. however, if there is an error condition (with the error flag bit (dq5/dq13) set to ?1?) the flash memory will re- turn to the read mode in 25 s after the reset in- struction is issued. the reset instruction is ignored when it is issued during a program or bulk erase cycle of the flash memory. the reset instruction aborts any on-go- ing sector erase cycle, and returns the flash memory to the normal read mode in 25 s. reset (reset ) pin a pulse on the reset (reset ) pin aborts any cy- cle that is in progress, and resets the flash mem- ory to the read mode. when the reset occurs during a program or erase cycle, the flash mem- ory takes up to 25 s to return to the read mode. it is recommended that the reset (reset ) pulse (except for power on reset, as described on page 74) be at least 25 s so that the flash memory is always ready for the mcu to fetch the bootstrap in- structions after the reset cycle is complete. sram the sram is enabled when sram select (rs0) from the dpld is high. sram select (rs0) can contain up to three product terms, allowing flexible memory mapping. the sram can be backed up using an external battery. the external battery should be connected to the voltage stand-by (v stby , pe6) line. if you have an external battery connected to the psd, the contents of the sram are retained in the event of a power loss. the contents of the sram are re- tained so long as the battery voltage remains at 2v or greater. if the supply voltage falls below the bat- tery voltage, an internal power switch-over to the battery occurs. pe7 can be configured as an output that indicates when power is being drawn from the external bat- tery. this battery-on indicator (vbaton, pe7) signal is high when the supply voltage falls below the battery voltage and the battery on voltage stand-by (v stby , pe6) is supplying power to the internal sram. sram select (rs0), voltage stand-by (v stby , pe6) and battery-on indicator ( vbaton, pe7) are all configured using psdsoft express.
35/100 psd4235g2 memory select signals the primary flash memory sector select (fs0- fs7), secondary flash memory sector select (csboot0-csboot3) and sram select (rs0) signals are all outputs of the dpld. they are de- fined using psdsoft express. the following rules apply to the equations for these signals: 1. primary flash memory and secondary flash memory sector select signals must not be larger than the physical sector size. 2. any primary flash memory sector must not be mapped in the same memory space as another flash memory sector. 3. a secondary flash memory sector must not be mapped in the same memory space as another secondary flash memory sector. 4. sram, i/o, and peripheral i/o spaces must not overlap. 5. a secondary flash memory sector may overlap a primary flash memory sector. in case of overlap, priority is given to the secondary flash memory sector. 6. sram, i/o, and peripheral i/o spaces may overlap any other memory sector. priority is given to the sram, i/o, or peripheral i/o. example fs0 is valid when the address is in the range of 8000h to bfffh, csboot0 is valid from 8000h to 9fffh, and rs0 is valid from 8000h to 87ffh. any address in the range of rs0 always accesses the sram. any address in the range of csboot0 greater than 87ffh (and less than 9fffh) auto- matically addresses secondary flash memory segment 0. any address greater than 9fffh ac- cesses the primary flash memory segment 0. you can see that half of the primary flash memory seg- ment 0 and one-fourth of secondary flash memory segment 0 cannot be accessed in this example. also note that an equation that defined fs1 to any- where in the range of 8000h to bfffh would not be valid. figure 8 shows the priority levels for all memory components. any component on a higher level can overlap and has priority over any component on a lower level. components on the same level must not overlap. level 1 has the highest priority and level 3 has the lowest. memory select configuration for mcus with separate program and data spaces the 80c51xa and compatible family of mcus, can be configured to have separate address spac- es for program memory (selected using program select enable (psen , cntl2)) and data memory (selected using read strobe (rd , cntl1)). any of the memories within the psd can reside in either space or both spaces. this is controlled through manipulation of the vm register that resides in the csiop space. the vm register is set using psdsoft express to have an initial value. it can subsequently be changed by the mcu so that memory mapping can be changed on-the-fly. for example, you may wish to have sram and pri- mary flash memory in the data space at boot-up, and secondary flash memory in the program space at boot-up, and later swap the secondary flash memory and primary flash memory. this is easily done with the vm register by using psdsoft express to configure it for boot-up and having the mcu change it when desired. table 25 describes the vm register. figure 8. priority level of memory and i/o components level 1 sram, i /o, or peripheral i /o level 2 secondary non-volatile memory highest priority lowest priority level 3 primary flash memory ai02867d
psd4235g2 36/100 separate space modes program space is separated from data space. for example, program select enable (psen , cntl2) is used to access the program code from the pri- mary flash memory, while read strobe (rd , cntl1) is used to access data from the secondary flash memory, sram and i/o port blocks. this configuration requires the vm register to be set to 0ch (see figure 9). combined space modes the program and data spaces are combined into one memory space that allows the primary flash memory, secondary flash memory, and sram to be accessed by either program select enable (psen , cntl2) or read strobe (rd , cntl1). for example, to configure the primary flash memory in combined space, bits 2 and 4 of the vm register are set to ?1? (see figure 10). 80c51xa memory map example see the application notes for examples. figure 9. 8031 memory modules - separate space figure 10. 8031 memory modules - combined space primary flash memory dpld secondary flash memory sram rs0 csboot0-3 fs0-fs7 cs cs cs oe oe rd psen oe ai02869c primary flash memory dpld secondary flash memory sram rs0 csboot0-3 fs0-fs7 rd cs cs cs rd oe oe vm reg bit 2 psen vm reg bit 0 vm reg bit 1 vm reg bit 3 vm reg bit 4 oe ai02870c
37/100 psd4235g2 page register the 8-bit page register increases the addressing capability of the mcu by a factor of up to 256. the contents of the register can also be read by the mcu. the outputs of the page register (pgr0- pgr7) are inputs to the dpld decoder and can be included in the sector select (fs0-fs7, csboot0-csboot3), and sram select (rs0) equations. if memory paging is not needed, or if not all eight page register bits are needed for memory paging, these bits may be used in the cpld for general logic. see application note an1154 . table 22 and figure 11 show the page register. the eight flip-flops in the register are connected to the internal data bus (d0-d7). the mcu can write to or read from the page register. the page reg- ister can be accessed at address location csiop + e0h. figure 11. page register memory id registers the 8-bit read-only memory status registers are included in the csiop space. the user can deter- mine the memory configuration of the psd device by reading the memory id0 and memory id1 reg- isters. the content of the registers is defined as shown in table 26 and table 27. reset d0 - d7 r/w d0 q0 q1 q2 q3 q4 q5 q6 q7 d1 d2 d3 d4 d5 d6 d7 page register pgr0 pgr1 pgr2 pgr3 dpld and cpld internal selects and logic pld pgr4 pgr5 pgr6 pgr7 ai02871b
psd4235g2 38/100 plds the plds bring programmable logic functionality to the psd. after specifying the logic for the plds using psdsoft express, the logic is programmed into the device and available upon power-up. the psd contains two plds: the decode pld (dpld), and the complex pld (cpld). the plds are briefly discussed in the next few paragraphs, and in more detail in the following sections. figure 12 shows the configuration of the plds. the dpld performs address decoding for internal components, such as memory, registers, and i/o ports select signals. the cpld can be used for logic functions, such as loadable counters and shift registers, state ma- chines, and encoding and decoding logic. these logic functions can be constructed using the 16 output macrocells (omc), 24 input macrocells (imc), and the and array. the cpld can also be used to generate external chip select (ecs0- ecs2) signals. the and array is used to form product terms. these product terms are specified using psdsoft express. an input bus consisting of 82 signals is connected to the plds. the signals are shown in table 32. the turbo bit in psd the plds in the psd4235g2 can minimize power consumption by switching to standby when inputs remain unchanged for an extended time of about 70 ns. resetting the turbo bit to ?0? (bit 3 of the pmmr0 register) automatically places the plds into standby if no inputs are changing. turning the turbo mode off increases propagation delays while reducing power consumption. see the sec- tion entitled ?power management?, on page 70, on how to set the turbo bit. additionally, five bits are available in the pmmr2 register to block mcu control signals from entering the plds. this reduces power consumption and can be used only when these mcu control signals are not used in pld logic equations. each of the two plds has unique characteristics suited for its applications. they are described in the following sections. table 32. dpld and cpld inputs note: 1. the address inputs are a19-a4 in 80c51xa mode. input source input name number of signals mcu address bus 1 a15-a0 16 mcu control signals cntl0-cntl2 3 reset rst 1 power-down pdn 1 port a input macrocells pa7-pa0 8 port b input macrocells pb7-pb0 8 port c input macrocells pc7-pc0 8 port d inputs pd3-pd0 4 port f inputs pf7-pf0 8 page register pgr7-pgr0 8 macrocell a feedback mcella.fb7-fb0 8 macrocell b feedback mcellb.fb7-fb0 8 flash memory program status bit ready/busy 1
39/100 psd4235g2 figure 12. pld diagram pld input bus 8 input macrocell & input ports direct macrocell input to mcu data bus csiop select sram select secondary non-volatile memory selects decode pld page register peripheral selects jtag select cpld pt alloc. macrocell alloc. mcella mcellb direct macrocell access from mcu data bus 24 input macrocell (port a,b,c) 16 output macrocell i/o ports primary flash memory selects 12 port d and port f inputs to port a to port b data bus 8 8 8 4 3 1 2 1 external chip selects to port c or port f 8 82 16 82 24 output macrocell feedback ai05737
psd4235g2 40/100 decode pld (dpld) the dpld, shown in figure 13, is used for decod- ing the address for internal and external compo- nents. the dpld can be used to generate the following decode signals: 8 sector select (fs0-fs7) signals for the primary flash memory (three product terms each) 4 sector select (csboot0-csboot3) signals for the secondary flash memory (three product terms each) 1 internal sram select (rs0) signal (three product terms) 1 internal csiop select (psd configuration register) signal 1 jtag select signal (enables jtag-isp on port e) 2 internal peripheral select signals (peripheral i/o mode). figure 13. dpld logic array note: 1. the address inputs are a19-a4 when in 80c51xa mode 2. additional address lines can be brought ino the psd via port a, b, c, d, or f. (inputs) (32) (8) (16) (1) pdn (apd output) i /o ports (port a,b,f) (8) pgr0 - pgr7 (8) mcellab.fb [7:0] (feedbacks) mcellbc.fb [7:0] (feedbacks) a [ 15:0 ] * (4) (3) pd [ 3:0 ] (ale,clkin,csi) cntrl [ 2:0 ] ( read/write control signals) (1) (1) reset rd_bsy rs0 csiop psel0 psel1 8 primary flash memory sector selects sram select i/o decoder select peripheral i/o mode select csboot 0 csboot 1 csboot 2 csboot 3 fs0 fs7 3 3 3 3 3 3 3 3 3 3 3 3 3 jtagsel ai05738 fs1 fs2 fs3 fs6 fs5 fs4 1 1 1 1
41/100 psd4235g2 complex pld (cpld) the cpld can be used to implement system logic functions, such as loadable counters and shift reg- isters, system mailboxes, handshaking protocols, state machines, and random logic. the cpld can also be used to generate eight external chip se- lect (ecs0-ecs7), routed to port c or port f. although external chip select (ecs0-ecs7) can be produced by any output macrocell (omc), these eight external chip select (ecs0-ecs7) on port c or port f do not consume any output mac- rocells (omc). as shown in figure 12, the cpld has the following blocks: 24 input macrocells (imc) 16 output macrocells (omc) product term allocator and array capable of generating up to 196 product terms four i/o ports. each of the blocks are described in the sections that follow. the input macrocells (imc) and output macrocells (omc) are connected to the psd internal data bus and can be directly accessed by the mcu. this enables the mcu software to load data into the output macrocells (omc) or read data from both the input and output macrocells (imc and omc). this feature allows efficient implementation of sys- tem logic and eliminates the need to connect the data bus to the and array as required in most standard pld macrocell architectures. figure 14. macrocell and i/o port i/o ports cpld macrocells input macrocells latched address out mux mux mux mux mux d d q q q g d qd wr wr pdr data product term allocator dir reg. select input product terms from other macrocells polarity select up to 10 product terms clock select pr di ld d/t ck cl q d/t/jk ff select pt clear pt clock global clock pt output enable ( oe ) macrocell feedback i/o port input ale/as pt input latch gate/clock mcu load pt preset mcu data in comb. /reg select pld input bus pld input bus mcu address / data bus macrocell out to mcu data load control and array cpld output i/o pin ai04945
psd4235g2 42/100 output macrocell (omc) eight of the output macrocells (omc) are con- nected to ports a pins and are named as mcella0- mcella7. the other eight macrocells are connect- ed to ports b pins and are named as mcellb0- mcellb7. the output macrocell (omc) architecture is shown in figure 15. as shown in the figure, there are native product terms available from the and array, and borrowed product terms available (if unused) from other output macrocells (omc). the polarity of the product term is controlled by the xor gate. the output macrocell (omc) can im- plement either sequential logic, using the flip-flop element, or combinatorial logic. the multiplexer selects between the sequential or combinatorial logic outputs. the multiplexer output can drive a port pin and has a feedback path to the and array inputs. the flip-flop in the output macrocell (omc) block can be configured as a d, t, jk, or sr type in the psdsoft express program. the flip-flop?s clock, preset, and clear inputs may be driven from a product term of the and array. alternatively, the external clkin (pd1) signal can be used for the clock input to the flip-flop. the flip-flop is clocked on the rising edge of clkin (pd1). the preset and clear are active high inputs. each clear input can use up to two product terms. table 33. output macrocell port and data bit assignments output macrocell port assignment native product ter ms maximum borrowed product terms data bit for loading or reading motorola 16-bit mcu for loading or reading mcella0 port a0 3 6 d0 d8 mcella1 port a1 3 6 d1 d9 mcella2 port a2 3 6 d2 d10 mcella3 port a3 3 6 d3 d11 mcella4 port a4 3 6 d4 d12 mcella5 port a5 3 6 d5 d13 mcella6 port a6 3 6 d6 d14 mcella7 port a7 3 6 d7 d15 mcellb0 port b0 4 5 d8 d0 mcellb1 port b1 4 5 d9 d1 mcellb2 port b2 4 5 d10 d2 mcellb3 port b3 4 5 d11 d3 mcellb4 port b4 4 6 d12 d4 mcellb5 port b5 4 6 d13 d5 mcellb6 port b6 4 6 d14 d6 mcellb7 port b7 4 6 d15 d7
43/100 psd4235g2 product term allocator the cpld has a product term allocator. psdsoft express, uses the product term allocator to bor- row and place product terms from one macrocell to another. the following list summarizes how prod- uct terms are allocated: mcella0-mcella7 all have three native product terms and may borrow up to six more mcellb0-mcellb3 all have four native product terms and may borrow up to five more mcellb4-mcellb7 all have four native product terms and may borrow up to six more. each macrocell may only borrow product terms from certain other macrocells. product terms al- ready in use by one macrocell are not available for another macrocell. if an equation requires more product terms than are available to it, then ?external? product terms are required, which consume other output macro- cells (omc). if external product terms are used, extra delay is added for the equation that required the extra product terms. this is called product term expansion. psdsoft express performs this expan- sion as needed. loading and reading the output macrocells (omc) the output macrocells (omc) block occupies a memory location in the mcu address space, as defined by the csiop (see the section entitled ?i/ o ports?, on page 58). the flip-flops in each of the 16 output macrocells (omc) can be loaded from the data bus by a mcu. loading the output mac- rocells (omc) with data from the mcu takes prior- ity over internal functions. as such, the preset, clear, and clock inputs to the flip-flop can be over- ridden by the mcu. the ability to load the flip-flops and read them back is useful in such applications as loadable counters and shift registers, mailbox- es, and handshaking protocols. data is loaded to the output macrocells (omc) on the trailing edge of write strobe (wr /wrl , cntl0). the omc mask register there is one mask register for each of the two groups of eight output macrocells (omc). the mask registers can be used to block the loading of data to individual output macrocells (omc). the default value for the mask registers is 00h, which allows loading of the output macrocells (omc). when a given bit in a mask register is set to a '1,' the mcu is blocked from writing to the as- sociated output macrocells (omc). for example, suppose mcella0-mcella3 are being used for a state machine. you would not want an mcu write to mcella to overwrite the state machine registers. therefore, you would want to load the mask register for mcella (mask macrocell a) with the value 0fh. the output enable of the omc the output macrocells (omc) can be connected to an i/o port pin as a pld output. the output en- able of each port pin driver is controlled by a single product term from the and array, ored with the direction register output. the pin is enabled upon power-up if no output enable equation is defined and if the pin is declared as a pld output in psd- soft express. if the output macrocell (omc) output is declared as an internal node and not as a port pin output in the psdabel file, then the port pin can be used for other i/o functions. the internal node feedback can be routed as an input to the and array.
psd4235g2 44/100 figure 15. cpld output macrocell pt allocator mask reg. pt clk pt pt pt clkin feedback ( .fb ) port input and array pld input bus mux mux polarity select ld in clr q pr din comb/reg select port driver input macrocell i/o pin internal data bus direction register clear ( .re ) programmable ff ( d / t/jk /sr ) wr enable ( .oe ) preset ( .pr ) rd macrocell cs ai04946
45/100 psd4235g2 input macrocells (imc) the cpld has 24 input macrocells (imc), one for each pin on ports a, b, and c. the architecture of the input macrocells (imc) is shown in figure 16. the input macrocells (imc) are individually config- urable, and can be used as a latch, register, or to pass incoming port signals prior to driving them onto the pld input bus. the outputs of the input macrocells (imc) can be read by the mcu through the internal data bus. the enable for the latch and clock for the register are driven by a multiplexer whose inputs are a product term from the cpld and array or the mcu address strobe (ale/as). each product term output is used to latch or clock four input macrocells (imc). port inputs 3-0 can be con- trolled by one product term and 7-4 by another. configurations for the input macrocells (imc) are specified by psdsoft express (see application note an1171 ). outputs of the input macrocells (imc) can be read by the mcu via the imc buffer. see the section entitled ?i/o ports?, on page 58. input macrocells (imc) can use address strobe (ale/as, pd0) to latch address bits higher than a15. any latched addresses are routed to the plds as inputs. input macrocells (imc) are particularly useful with handshaking communication applications where two processors pass data back and forth through a common mailbox. figure 18 shows a typical con- figuration where the master mcu writes to the port a data out register. this, in turn, can be read by the slave mcu via the activation of the ?slave- read? output enable product term. the slave can also write to the port a input mac- rocells (imc) and the master can then read the in- put macrocells (imc) directly. note that the ?slave-read? and ?slave-wr? signals are product terms that are derived from the slave mcu inputs read strobe (rd , cntl1), write strobe (wr /wrl , cntl0), and slave_cs. figure 16. input macrocell output macrocells a and macrocells b pt pt feedback and array pld input bus port driver i/o pin internal data bus direction register mux mux ale/as pt q q d d g latch input macrocell enable ( .oe ) d ff input macrocell _ rd ai04926
psd4235g2 46/100 external chip select the cpld also provides eight external chip se- lect (ecs0-ecs7) outputs that can be used to se- lect external devices. each external chip select (ecs0-ecs7) consists of one product term that can be configured active high or low. the output enable of the pin is controlled by either the output enable product term or the direction register. (see figure 17.) figure 17. external chip select signal figure 18. handshaking communication using input macrocells pld input bus polarity bit port pin ecs pt ecs to port c or f enable (.oe) pt direction register cpld and array port c or port f ai04927 master mcu mcu -rd mcu -rd mcu -wr slave ? wr slave ? cs mcu -wr d [ 7:0 ] d [ 7:0 ] cpld dq qd port a data out register port a input macrocell port a slave ? read slave mcu rd wr ai02877c psd
47/100 psd4235g2 mcu bus interface the ?no-glue logic? mcu bus interface block can be directly connected to most popular mcus and their control signals. key 16-bit mcus, with their bus types and control signals, are shown in table 34. the mcu interface type is specified using the psdsoft express. table 34. mcus and their control signals note: 1. unused cntl2 pin can be configured as cpld input. other unused pins (pd3-pd0, pf3-pf0) can be configured for other i/o f unc- tions. 2. ale/as input is optional for mcus with a non-multiplexed bus mcu cntl0 cntl1 cntl2 pd3 pd0 2 adio0 pf3-pf0 68302, 68306, mmc2001 r/w lds uds (note 1 ) as ? (note 1 ) 68330, 68331, 68332, 68340 r/w ds siz0 (note 1 ) as a0 (note 1 ) 68lc302, mmc2001 wel oe ?weh as ? (note 1 ) 68hc16 r/w ds siz0 (note 1 ) as a0 (note 1 ) 68hc912 r/w elstrb dbe ea0 (note 1 ) 68hc812 3 r/w elstrb (note 1 )(note 1 ) a0 (note 1 ) 80196 wr rd bhe (note 1 ) ale a0 (note 1 ) 80196sp wrl rd (note 1 ) wrh ale a0 (note 1 ) 80186 wr rd bhe (note 1 ) ale a0 (note 1 ) 80c161, 80c164-80c167 wr rd bhe (note 1 ) ale a0 (note 1 ) 80c51xa wrl rd psen wrh ale a4/d0 a3-a1 h8/300 wrl rd (note 1 ) wrh as a0 ? m37702m2 r/w e bhe (note 1 ) ale a0 (note 1 )
psd4235g2 48/100 psd interface to a multiplexed bus figure 19 shows an example of a system using a mcu with a 16-bit multiplexed bus and a psd4235g2. the adio port on the psd is con- nected directly to the mcu address/data bus. ad- dress strobe (ale/as, pd0) latches the address signals internally. latched addresses can be brought out to port e, f or g. the psd drives the adio data bus only when one of its internal re- sources is accessed and read strobe (rd , cntl1) is active. should the system address bus exceed sixteen bits, ports a, b, c, or f may be used as additional address inputs. figure 19. an example of a typical 16-bit multiplexed bus interface mcu wr rd bhe ale reset ad [ 7:0 ] ad[15:8] 1 a [ 15: 8 ] a [ 7: 0 ] adio port port f port g port a wr ( cntrl0 ) rd ( cntrl1 ) bhe ( cntrl2 ) rst ale ( pd0 ) port d ( optional ) ( optional ) psd ai04928b a [ 23:16 ] ( optional ) or a[15:8]
49/100 psd4235g2 psd interface to a non-multiplexed 8-bit bus figure 20 shows an example of a system using a mcu with a 16-bit non-multiplexed bus and a psd4235g2. the address bus is connected to the adio port, and the data bus is connected to ports f and g. ports f and g are in tri-state mode when the psd is not accessed by the mcu. should the system address bus exceed sixteen bits, ports a, b, or c may be used for additional address inputs. figure 20. an example of a typical 16-bit non-multiplexed bus interface mcu wr rd bhe ale reset d [ 15:0 ] a [ 15:0 ] d[15:8] 1 d [ 7:0 ] adio port port f port g port a wr ( cntrl0 ) rd ( cntrl1 ) bhe ( cntrl2 ) rst ale ( pd0 ) port d psd ai04929b a [ 23:16 ] ( optional )
psd4235g2 50/100 data byte enable reference mcus have different data byte orientations. table 35 to table 38 show how the psd4235g2 inter- prets byte/word operations in different bus write configurations. even-byte refers to locations with address a0 equal to '0,' and odd byte as locations with a0 equal to '1.' table 35. 16-bit data bus with bhe mcu bus interface examples figure 21 to figure 26 show examples of the basic connections between the psd4235g2 and some popular mcus. the psd4235g2 control input pins are labeled as to the mcu function for which they are configured. the mcu bus interface is specified using psdsoft express. the voltage stand-by (v stby , pe6) line should be held at ground if not in use. table 36. 16-bit data bus with wrh and wrl table 37. 16-bit data bus with siz0, a0 (motorola mcu) table 38. 16-bit data bus with lds, uds (motorola mcu) bhe a0 d15-d8 d7-d0 0 0 odd byte even byte 0 1 odd byte ? 1 0 ? even byte wrh wrl d15-d8 d7-d0 0 0 odd byte even byte 0 1 odd byte ? 1 0 ? even byte siz0 a0 d15-d8 d7-d0 0 0 even byte odd byte 1 0 even byte ? 1 1 ? odd byte wrh wrl d15-d8 d7-d0 0 0 even byte odd byte 1 0 even byte ? 0 1 ? odd byte
51/100 psd4235g2 80c196 and 80c186 in figure 21, the intel 80c196 mcu, which has a 16-bit multiplexed address/data bus, is shown connected to a psd4235g2. the read strobe (rd , cntl1), and write strobe (wr /wrl , cntl0) signals are connected to the cntl pins. when bhe is not used, the psd can be configured to receive wrl and write enable high-byte (wrh /dbe, pd3) from the mcu. higher address inputs (a16-a19) can be routed to ports a, b, or c as input ot the pld. the amd 80186 family has the same bus connec- tion to the psd as the 80c196. figure 21. interfacing the psd with an 80c196 x1 x2 p1.0/epa0/t2clk p1.1/epa1 p1.2/epa2/t2dir p1.3/epa3 p1.4/epa4 p1.5/epa5 p1.6/epa6 p1.7/epa7 p3.0/ad0 p3.1/ad1 p3.2/ad2 p3.3/ad3 p3.4/ad4 p3.5/ad5 p3.6/ad6 p3.7/ad7 pf0 pf1 pf2 pf3 pf4 pf5 pf6 pf7 pg0 pg1 pg2 pg3 pg4 pg5 pg6 pg7 pa0 pa2 pa1 pa3 pa4 pa5 pa6 pa7 p4.0/ad8 p4.1/ad9 p4.2/ad10 p4.3/ad11 p4.4/ad12 p4.5/ad13 p4.6/ad14 p4.7/ad15 adio0 adio1 adio2 adio3 adio4 adio5 adio6 adio7 adio8 adio9 adio10 adio11 adio12 adio13 adio14 adio15 cntl0 (wr) cntl1 (rd) cntl2 (bhe) pd0 (ale) pd1 (clkin) pd2 (csi) reset rd/p5.3 wr/wrl/p5.2 bhe/wrh/p5.5 ale/adv/p5.0 inst/p5.1 slpint/p5.4 reset 31 32 33 34 35 36 37 38 3 19 18 57 56 55 54 53 52 51 50 ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 4 5 6 7 10 11 12 13 14 15 16 17 18 19 20 59 39 60 40 79 80 1 21 22 23 24 25 26 27 28 psd 80c196nt a19-a16 a [ 19:16 ] 7 9 8 4 rd wr bhe ale 3 1 reset 51 52 53 54 55 56 57 58 ai04930 ad15-ad0 ad [ 15:0 ] pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 pc0 pc2 pc1 pc3 pc4 pc5 pc6 pc7 61 62 63 64 65 66 67 68 41 42 43 44 45 46 47 48 pd3 (wrh) 2 pe0 (tms) pe1 (tck/st) pe2 (tdi) pe3 (tdo) pe4 (tstat/rdy) pe5 (terr) pe6 (vstby) pe7 (vbaton) 71 72 73 74 75 76 77 78 8 30495070 gnd gnd gnd gnd gnd 92969 vcc vcc vcc vcc ad8 ad9 ad10 ad11 ad12 ad13 ad14 ad15 3 4 5 6 7 10 11 12 13 14 15 16 17 18 19 20 ep.0/a16 ep.1/a17 ep.2/a18 ep.3/a19 14 13 12 11 31 buswidth/p5.7 10 ea 33 reset ready/p5.6 2 p2.0/tx/pvr p2.1/rxd/pale p2.2/exint/prog p2.3/intb p2.4/intintout p2.5/hld p2.6/hlda/cpver p2.7/clkout/pac 36 37 38 39 40 41 42 43 p6.0/epa8 p6.1/epa9 p6.2/t1clk p6.3/t1dir p6.4/sc0 p6.5/sd0 p6.6/sc1 p6.7/sd1 58 59 60 61 62 63 64 65 nmi vref vpp angnd ach4/p0.4/pmd.0 ach5/p0.5/pmd.1 ach6/p0.6/pmd.2 ach7/p0.7/pmd.3 32 49 6 48 44 45 46 47 a16 a17 a18 a19 a16 a17 a18 a19
psd4235g2 52/100 mc683xx and mc68hc16 figure 22 shows a mc68331 with a 16-bit non- multiplexed data bus and 24-bit address bus. the data bus from the mc68331 is connected to port f (d0-d7) and port g (d8-d15). the siz0 and a0 in- puts determine the high/low byte selection. the r/ w, ds and siz0 signals are connected to the cntl0-cntl2 pins. the mc68hc16, and other members of the mc683xx family, has the same bus connection to the psd as the mc68331 shown in figure 22. figure 22. interfacing the psd with an mc68331 vcc_bar d[15:0] a16 a5 d1 d13 ds\ as a8 d12 a1 a18 a19 a23 d4 d12 d8 a22 d7 d3 a[23:0] d3 d11 a16 a17 d14 d13 a3 d2 d5 a19 a0 a12 d2 a4 r/w\ d6 d5 reset\ a7 a2 a13 a14 a15 d7 d9 d10 d15 d4 a17 a6 siz0 d10 d15 a18 a21 a11 d0 d1 d6 d11 d14 d9 d0 a20 d8 a9 a10 mc68331 a1 20 a2 21 a3 22 a4 23 a5 24 a6 25 a7 26 a8 27 a9 30 a10 31 a11 32 a12 33 a13 35 a14 36 a15 37 a16 38 a17 41 a18 42 a19_cs6/ 121 a20_cs7/ 122 a21_cs8/ 123 a22_cs9/ 124 a23_cs10/ 125 r_w 79 as 82 d0 111 d1 110 d2 109 d4 105 d5 104 d6 103 d7 102 d8 100 d9 99 d10 98 d11 97 d13 93 d14 92 d15 91 a0 90 d3 108 d12 94 ds 85 siz0 81 siz1 80 csboot/ 112 br_cs0/ 113 bg_cs1/ 114 bgack_cs2/ 115 fc0_cs3/ 118 fc1_cs4/ 119 fc2_cs5/ 120 reset 68 dsack0 89 dsack1 88 clkout 66 irq1 77 irq2 76 irq3 75 irq4 74 irq5 73 irq6 72 irq7 71 psd adio0 3 adio1 4 adio2 5 adio3 6 adio4 7 adio5 10 adio6 11 adio7 12 adio9 14 adio10 15 adio11 16 adio12 17 adio13 18 adio14 19 adio15 20 pf0 31 pf1 32 pf2 33 pf3 34 pf4 35 pf5 36 pf6 37 pf7 38 pg1 22 pg2 23 pg3 24 pg4 25 pg5 26 pg6 27 pg7 28 pa5 56 pa6 57 pa7 58 cntl0(r/w) 59 cntl1(ds) 60 cntl2 (siz0) 40 pd0 (as) 79 reset 39 adio8 13 pg0 21 pa3 54 pa4 55 pa2 53 pa0 51 pa1 52 pb0 61 pb1 62 pb2 63 pb3 64 pb4 65 pb5 66 pb6 67 pb7 68 pc0 41 pc1 42 pc2 43 pc3 44 pc4 45 pc5 46 pc6 47 pc7 48 pe0 (tms) 71 pe1 (tck/st) 72 pe2 (tdi) 73 pe3 (tdo) 74 pe4 (tstat/rdy) 75 pe5 (terr) 76 pe7 (vbaton) 78 v cc 29 v cc 69 v cc 9 g n d 50 g n d 49 g n d 30 g n d 8 g n d 70 pd2 (csi) 1 pd1 (clkin) 80 pd3 2 pe6 (vstby) 77 reset\ a[23:0] d[15:0] ai04951b
53/100 psd4235g2 80c51xa the philips 80c51xa mcu has a 16-bit multi- plexed bus with burst cycles. address bits (a3-a1) are not multiplexed, while (a19-a4) are multi- plexed with data bits (d15-d0). the psd4235g2 supports the 80c51xa burst mode. the wrh signal is connected to pd3, and whl is connected to cntl0. the rd and psen signals are connected to the cntl1 and cntl2 pins. figure 23 shows the schematic diagram. the 80c51xa improves bus throughput and per- formance by issuing burst cycles to fetch codes from memory. in burst cycles, address a19-a4 are latched internally by the psd, while the 80c51xa drives the a3-a1 signals to fetch sequentially up to 16 bytes of code. the psd access time is then measured from address a3-a1 valid to data in val- id. the psd bus timing requirement in a burst cy- cle is identical to the normal bus cycle, except the address setup and hold time with respect to ad- dress strobe (ale/as, pd0) is not required. figure 23. interfacing the psd with an 80c51xa-g3 vcc_bar vcc_bar d[15:0] wrl\ rd\ psen\ ale a4d0 a5d1 a6d2 a7d3 a8d4 a9d5 a10d6 a11d7 a12d8 a13d9 a14d10 a15d11 a16d12 a17d13 a18d14 a19d15 reset\ reset\ a3 a2 a1 wrh\ a[3:1] a1 a2 a3 u3 crystal psd adio0 3 adio1 4 adio2 5 adio3 6 adio4 7 adio5 10 adio6 11 adio7 12 adio9 14 adio10 15 adio11 16 adio12 17 adio13 18 adio14 19 adio15 20 pf0 31 pf1 32 pf2 33 pf3 34 pf4 35 pf5 36 pf6 37 pf7 38 pg1 22 pg2 23 pg3 24 pg4 25 pg5 26 pg6 27 pg7 28 pa5 56 pa6 57 pa7 58 cntl0(wr) 59 cntl1(rd) 60 cntl2(psen) 40 pd0 (ale) 79 reset 39 adio8 13 pg0 21 pa3 54 pa4 55 pa2 53 pa0 51 pa1 52 pb0 61 pb1 62 pb2 63 pb3 64 pb4 65 pb5 66 pb6 67 pb7 68 pc0 41 pc1 42 pc2 43 pc3 44 pc4 45 pc5 46 pc6 47 pc7 48 pe0 (tms) 71 pe1 (tck/st) 72 pe2 (tdi) 73 pe3 (tdo) 74 pe4 (tstat/rdy) 75 pe5 (terr) 76 pe7 (vbaton) 78 vcc 29 vcc 69 vcc 9 g nd 50 g nd 49 g nd 30 g nd 8 g nd 70 pd2 (csi) 1 pd1 (clkin) 80 pd3 (wrh) 2 pe6 (vstby) 77 xa-g3 a0/wrh 2 a1 3 a2 4 a3 5 a4d0 43 a5d1 42 a6d2 41 a7d3 40 a8d4 39 a9d5 38 a10d6 37 a11d7 36 a12d8 24 a13d9 25 a14d10 26 a15d11 27 a16d12 28 a17d13 29 a18d14 30 a19d15 31 psen 32 rd 19 wrl 18 ale 33 rst 10 int0 14 int1 15 ea/wait 35 busw 17 xtal1 21 xtal2 20 rxd0 11 txd0 13 rxd1 6 txd1 7 t2ex 9 t2 8 t0 16 d[15:0] a[3:1] ai04952b
psd4235g2 54/100 h8/300 figure 24 shows an hitachi h8/2350 with a 16-bit non-multiplexed data bus, and a 24-bit address bus. the h8 data bus is connected to port f (d0- d7) and port g (d8-d15). the wrh signal is connected to pd3, and whl is connected to cntl0. the rd signal is connected to cntl1. the connection to the address strobe (as) signal is optional, and is required if the ad- dresses are to be latched. figure 24. interfacing the psd with an h83/2350 vcc_bar as reset\ rd\ reset\ wrl\ a21 a3 a[23:0] a11 a1 a9 a14 a15 a20 a5 a8 a13 a10 a7 a18 a19 a17 a2 a16 a4 a6 a12 a0 d4 d9 d10 d15 d8 d7 d[15:0] d2 d5 d0 d11 d13 d3 d14 d1 d6 d12 wrh\ a22 a23 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 a16 a17 a18 a19 u3 crystal h8s/2655 pc0/a0 2 pc1/a1 3 pc2/a2 4 pc3/a3 5 pc4/a4 7 pc5/a5 8 pc6/a6 9 pc7/a7 10 pb0/a8 11 pb1/a9 12 pb2/a10 13 pb3/a11 14 pb4/a12 16 pb5/a13 17 pb6/a14 18 pb7/a15 19 pa0/a16 20 pa1/a17 21 pa2/a18 22 pa3/a19 23 pa4/a20/irq4 25 pa5/a21/irq5 26 pa6/a22/irq6 27 pa7/a23/irq7 28 cs7/irq3 29 cs6/irq2 30 irq1 31 irq0 32 rxd0 55 txd0 53 sck0 57 rxd1 56 txd1 54 sck1 58 rxd2 90 txd2 89 sck2 91 pf0/breq 88 pf1/back 87 pf2/lcas/wait/b 86 nmi 74 po0/tioca3 71 po1/tiocb3 70 po2/tiocc3/tmri 69 po3/tiocd3/tmci 68 po4/tioca4/tmri 67 po5/tiocb4/tmrc 66 po6/tioca5/tmro 65 po7/tiocb5/tmro 64 dreq/cs4 60 tend0/cs5 61 dreq1 62 tend1 63 pe0/d0 34 pe0/d1 35 pe0/d2 36 pe0/d3 37 pe0/d4 39 pe0/d5 40 pe0/d6 41 pe0/d7 42 pd0/d8 43 pd1/d9 44 pd2/d10 45 pd3/d11 46 pd4/d12 48 pd5/d13 49 pd6/d14 50 pd7/d15 51 rd 83 lwr 85 hwr 84 as 82 pf0/phi0 80 reset 73 wdtovf 72 mod0 113 mod1 114 mod2 115 stby 75 extal 78 xtal 77 pg0/cas/oe 116 pg1/cs3 117 pg2/cs2 118 pg3/cs1 119 pg4/cs0 120 po8/tioca0/dack 112 po9/tiocb0/dack 111 po10/tiocc0/tcl 110 po11/tiocd0/tcl 109 po12/tioca1 108 po13/tiocb1/tcl 107 po14/tioca2 106 po15/tiocb2/tcl 105 an0 95 an1 96 an2 97 an3 98 an4 99 an5 100 an6/da0 101 an7/da1 102 adtrg 92 psd adio0 3 adio1 4 adio2 5 adio3 6 adio4 7 adio5 10 adio6 11 adio7 12 adio9 14 adio10 15 adio11 16 adio12 17 adio13 18 adio14 19 adio15 20 pf0 31 pf1 32 pf2 33 pf3 34 pf4 35 pf5 36 pf6 37 pf7 38 pg1 22 pg2 23 pg3 24 pg4 25 pg5 26 pg6 27 pg7 28 pa5 56 pa6 57 pa7 58 cntl0(wrl) 59 cntl1(rd) 60 cntl2 40 pd0 (as) 79 reset 39 adio8 13 pg0 21 pa3 54 pa4 55 pa2 53 pa0 51 pa1 52 pb0 61 pb1 62 pb2 63 pb3 64 pb4 65 pb5 66 pb6 67 pb7 68 pc0 41 pc1 42 pc2 43 pc3 44 pc4 45 pc5 46 pc6 47 pc7 48 pe0 (tms) 71 pe1 (tck/st) 72 pe2 (tdi) 73 pe3 (tdo) 74 pe4 (tstat/rdy) 75 pe5 (terr) 76 pe7 (vbaton) 78 v cc 29 v cc 69 v cc 9 g n d 50 g n d 49 g n d 30 g n d 8 g n d 70 pd2 (csi) 1 pd1 (clkin) 80 pd3 (wrh) 2 pe6 (vstby) 77 a[23:0] d[15:0] ai04953b
55/100 psd4235g2 mmc2001 the motorola mcore mmc2001 mcu has a mod input pin that selects interal or external boot rom. the psd can be configured as the external flash boot rom or as extension to the internal rom. the mmc2001 has a 16-bit external data bus and 20 address lines with external chip select signals. the chip select control registers allow the user to customize the bus interface and timing to fit the individual system requirement. a typical interface configuaration to the psd is shown in figure 25. the mmc2001?s r/w signal is conneced to the cntl0 pin, while eb0 and eb1 (enable byte-0 and enable byte-1) are connected to the cntl1 (uds ) and cntl2 (lds ) pins. the wen bit in the chip select control register should be set to ?1? to ter- minate the eb0 -eb1 earlier to provide the wrtie data hold time for the psd. the wsc and wws bits in the control register are set to wait states that meet the psd access time requirement. another option is to configure the eb0 and eb1 as wrl and wrh signals. in this case, the psd con- trol setting will be: oe , wrl , wrh where oe is the read signal for the mmc2001. c16x family the psd supports infineon?s c16x family of mcus (c161-c167) in both the multiplexed and non-multiplexed bus configuration. in figure 26, the c167cr is shown connected to the psd in a multiplexed bus configuration. the control signals from the mcu are wr , rd , bhe and ale, and are routed to the corresponding psd pins. the c167 has another control signal setting (rd , wrl , wrh , ale) which is also supported by the psd.
psd4235g2 56/100 figure 25. interfacing the psd with an mmc2001 vcc_bar vcc_bar a16 ale ad14 ad10 ad6 a17 a19 rd\ ad13 ad9 ad5 ad1 reset\ a19 bhe\ ad7 a[19:16] a17 ad[15:0] ad12 ad4 ad2 a18 wr\ ad15 ad8 a18 ad11 a16 reset\ ad3 ad0 u3 crystal psd adio0 3 adio1 4 adio2 5 adio3 6 adio4 7 adio5 10 adio6 11 adio7 12 adio9 14 adio10 15 adio11 16 adio12 17 adio13 18 adio14 19 adio15 20 pf0 31 pf1 32 pf2 33 pf3 34 pf4 35 pf5 36 pf6 37 pf7 38 pg1 22 pg2 23 pg3 24 pg4 25 pg5 26 pg6 27 pg7 28 pa5 56 pa6 57 pa7 58 cntl0(wr) 59 cntl1(rd) 60 cntl2(bhe) 40 pd0 (ale) 79 reset 39 adio8 13 pg0 21 pa3 54 pa4 55 pa2 53 pa0 51 pa1 52 pb0 61 pb1 62 pb2 63 pb3 64 pb4 65 pb5 66 pb6 67 pb7 68 pc0 41 pc1 42 pc2 43 pc3 44 pc4 45 pc5 46 pc6 47 pc7 48 pe0 (tms) 71 pe1 (tck/st) 72 pe2 (tdi) 73 pe3 (tdo) 74 pe4 (tstat/rdy) 75 pe5 (terr) 76 pe7 (vbaton) 78 v c c 2 9 v c c 6 9 v c c 9 g n d 5 0 g n d 4 9 g n d 3 0 g n d 8 g n d 7 0 pd2 (csi) 1 pd1 (clkin) 80 pd3 (wrh) 2 pe6 (vstby) 77 infineon c167cr ad0 100 ad1 101 v c c 1 0 9 ad2 102 ad3 103 ad4 104 ad5 105 ad6 106 ad7 107 ad8 108 ad9 111 ad10 112 ad11 113 ad12 114 ad13 115 ad14 116 ad15 117 ea 99 ale 98 ready 97 wr/wrl 96 rd 95 v c c 9 3 xtal1 138 xtal2 137 rstin 140 rstout 141 nmi 142 p4.0/a16 85 a17 86 a18 87 a19 88 a20 89 a21 90 a22 91 p4.7/a23 92 p3.0/t0in 65 p3.1/t6out 66 p3.2/capin 67 p3.3/t3out 68 p3.4/t3eud 69 p3.5/t4in 70 p3.6/t3in 73 p3.7/t2in 74 p3.8/mrst 75 p3.9/mtsr 76 p3.10/txd0 77 p3.11/rxd0 78 p3.12/bhe/wrh 79 p3.13/sclk 80 p3.15/clkout 81 p1l0 118 p1l1 119 p1l2 120 p1l3 121 p1l4 122 p1l5 123 p1l6 124 p1l7 125 p1h0 128 p1h1 129 p1h2 130 p1h3 131 p1h4 132 p1h5 133 p1h6 134 p1h7 135 p2.0/cc0io 47 p2.1/cc1io 48 p2.2/cc2io 49 p2.3/cc3io 50 p2.4/cc4io 51 p2.5/cc5io 52 p2.6/cc6io 53 p2.7/cc7io 54 p2.8/cc8io/ex0in 57 p2.9/cc9io/ex1in 58 p2.10/cc10io/ex2in 59 p2.11/cc11io/ex3in 60 p2.12/cc12io/ex4in 61 p2.13/cc13io/ex5in 62 p2.14/cc14io/ex6in 63 p2.15/cc15io/ex7in 64 p5.0/an0 27 p5.1/an1 28 p5.2/an2 29 p5.3/an3 30 p5.4/an4 31 p5.5/an5 32 p5.6/an6 33 p5.7/an7 34 p5.8/an8 35 p5.9/an9 36 p5.10/an10/t6ued 39 p5.11/an11/t5ued 40 p5.12/an12/t6in 41 p5.13/an13/t5in 42 p5.14/an14/t4ued 43 p5.15/an15/t2ued 44 p6.0/!cs0 1 p6.1/!cs1 2 p6.2/!cs2 3 p6.3/!cs3 4 p6.4/!cs4 5 p6.5/!hold 6 p6.6/!hlda 7 p6.7/!breq 8 p7.0/pout0 19 p7.1/pout1 20 p7.2/pout2 21 p7.3/pout3 22 p7.4/cc28io 23 p7.5/cc29io 24 p7.6/cc30io 25 p7.7/cc31io 26 p8.0/cc16io 9 p8.1/cc17io 10 p8.2/cc18io 11 p8.3/cc19io 12 p8.4/cc20io 13 p8.5/cc21io 14 p8.6/cc22io 15 p8.7/cc23io 16 v s s 1 4 3 v s s 1 3 9 v s s 1 2 7 v s s 1 1 0 v s s 9 4 v s s 8 3 v s s 7 1 v s s 5 5 v s s 4 5 v s s 1 8 a g n d 3 8 v c c 1 4 4 v c c 1 3 6 v c c 1 2 6 v c c 8 2 v c c 7 2 v c c 1 7 v c c 5 6 v c c 4 6 vref 37 adio[15:0] a[19:16] ai04954b
57/100 psd4235g2 figure 26. interfacing the psd with a c167cr xtal1 xtal2 p8.0/cc16io p8.1/cc17io p8.2/cc18io p8.3/cc19io p8.4/cc20io p8.5/cc21io p8.6/cc22io p8.7/cc23io ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 pf0 pf1 pf2 pf3 pf4 pf5 pf6 pf7 pg0 pg1 pg2 pg3 pg4 pg5 pg6 pg7 pa0 pa2 pa1 pa3 pa4 pa5 pa6 pa7 ad8 ad9 ad10 ad11 ad12 ad13 ad14 ad15 adio0 adio1 adio2 adio3 adio4 adio5 adio6 adio7 adio8 adio9 adio10 adio11 adio12 adio13 adio14 adio15 cntl0 (wr) cntl1 (rd) cntl2 (bhe) pd0 (ale) pd1 (clkin) pd2 (csi) reset rd wr/wrl p312/bhe/wrh ale reset 31 32 33 34 35 36 37 38 3 138 137 9 10 11 12 13 14 15 16 ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 4 5 6 7 10 11 12 13 14 15 16 17 18 19 20 59 39 60 40 79 80 1 21 22 23 24 25 26 27 28 psd c167cr a19-a16 a [ 19:16 ] 95 96 79 98 rd wr bhe ale reset 51 52 53 54 55 56 57 58 ai04955 ad15-ad0 ad [ 15:0 ] pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 pc0 pc2 pc1 pc3 pc4 pc5 pc6 pc7 61 62 63 64 65 66 67 68 41 42 43 44 45 46 47 48 pd3 (wrh) 2 pe0 (tms) pe1 (tck/st) pe2 (tdi) pe3 (tdo) pe4 (tstat/rdy) pe5 (terr) pe6 (vstby) pe7 (vbaton) 71 72 73 74 75 76 77 78 8 30495070 gnd gnd gnd gnd gnd 92969 vcc vcc vcc vcc ad8 ad9 ad10 ad11 ad12 ad13 ad14 ad15 100 101 102 103 104 105 106 107 108 111 112 113 114 115 116 117 p4.0/a16 p4.1/a17 p4.2/a18 p4.3/a19 85 86 87 88 140 ea 99 rstin p7.0/pout0 p7.1/pout1 p7.2/pout2 p7.3/pout3 p7.4/cc28io p7.5/cc29io p7.6/cc30io p7.7/cc31io 19 20 21 22 23 24 25 26 p6.0/!cs0 p6.1/!cs1 p6.2/!cs2 p6.3/!cs3 p6.4/!cs4 p6.5/!hold p6.6/!hlda p6.7/!breq 1 2 3 4 5 6 7 8 a16 a17 a18 a19 a16 a17 a18 a19 p5.8/an8 p5.9/an9 p5.10/an10/t6ued p5.11/an11/t5ued p5.12/an12/t6in p5.13/an13 p5.14/an14/t4ued p5.15/an15/t2ued 35 36 39 40 41 42 43 44 p5.0/an0 p5.1/an1 p5.2/an2 p5.3/an3 p5.4/an4 p5.5/an5 p5.6/an6 p5.7/an7 27 28 29 30 31 32 33 34 p3.8/mrst p3.9/mtsr p3.10/txd0 p3.11/rxd0 p3.12 p3.13/sclk p3.15/clkout 75 76 77 78 79 80 81 p3.0/t0in p3.1/t6out p3.2/capin p3.3/t3out p3.4/t3ued p3.5/t4in p3.6/t3in p3.7/t2in 65 66 67 68 69 70 73 74 vref ready 37 97 p1h7 p1h6 p1h5 p1h4 p1h3 p1h2 p1h1 p1h0 135 134 133 132 131 130 129 128 p1l7 p1l6 p1l5 p1l4 p1l3 p1l2 p1l1 p1l0 125 124 123 122 121 120 119 118 p2.0/cc0io p2.1/cc1io p2.2/cc2io p2.3/cc3io p2.4/cc4io p2.5/cc5io p2.6/cc6io p2.7/cc7io 47 48 49 50 51 52 53 54 p2.8/cc8io/ex0in p2.9/cc9io/ex1in p2.10/cc10io/ex2in p2.11/cc11io/ex3in p2.12/cc12io/ex4in p2.13/cc13io/ex5in p2.14/cc14io/ex6in p2.15/cc15io/ex7in 57 58 59 60 61 62 63 64 rstout nmi 141 142 p4.4/a20 p4.5/a21 p4.6/a22 p4.7/a23 89 90 91 92 143139127110 94 83 71 55 45 18 vssvssvssvssvssvssvssvssvssvss agnd 38 144136129109 93 82 72 56 46 17 vccvccvccvccvccvccvccvccvccvcc vcc
psd4235g2 58/100 i/o ports there are seven programmable i/o ports: ports a, b, c, d, e, f and g. each port pin is individually user configurable, thus allowing multiple functions per port. the ports are configured using psdsoft express or by the mcu writing to on-chip registers in the csiop space. the topics discussed in this section are: general port architecture port operating modes port configuration registers (pcr) port data registers individual port functionality. general port architecture. the general archi- tecture of the i/o port block is shown in figure 27. individual port architectures are shown in figure 29 to figure 31. in general, once the purpose for a port pin has been defined, that pin is no longer available for other purposes. exceptions are not- ed. as shown in figure 27, the ports contain an output multiplexer whose select signals are driven by the configuration bits in the control registers (ports e, f and g only) and psdsoft express configuration. inputs to the multiplexer include the following: output data from the data out register latched address outputs cpld macrocell output external chip select from the cpld. the port data buffer (pdb) is a tri-state buffer that allows only one source at a time to be read. the port data buffer (pdb) is connected to the internal data bus for feedback and can be read by the mcu. the data out and macrocell outputs, direc- tion register and control register, and port pin in- put are all connected to the port data buffer (pdb). the port pin?s tri-state output driver enable is con- trolled by a two input or gate whose inputs come from the cpld and array enable product term and the direction register. if the enable product term of any of the array outputs are not defined and that port pin is not defined as a cpld output in the psdabel file, the direction register has sole control of the buffer that drives the port pin. the contents of these registers can be altered by the mcu. the port data buffer (pdb) feedback path allows the mcu to check the contents of the registers. ports a, b, and c have embedded input macro- cells (imc). the input macrocells (imc) can be configured as latches, registers, or direct inputs to the plds. the latches and registers are clocked by address strobe (ale/as, pd0) or a product term from the pld and array. the outputs from the input macrocells (imc) drive the pld input bus and can be read by the mcu. see the section en- titled ?input macrocell?, on page 45. port operating modes the i/o ports have several modes of operation. some modes can be defined using psdsoft ex- press, some by the mcu writing to the registers in csiop space, and some by both. the modes that can only be defined using psdsoft express must be programmed into the device and cannot be changed unless the device is reprogrammed. the modes that can be changed by the mcu can be done so dynamically at run-time. the pld i/o, data port, address input, peripheral i/o and mcu reset modes are the only modes that must be de- fined before programming the device. all other modes can be changed by the mcu at run-time. see application note an1171 for more detail. table 39 summarizes which modes are available on each port. table 40 shows how and where the different modes are configured. each of the port operating modes are described in the following sections.
59/100 psd4235g2 figure 27. general i/o port architecture internal data bus data out reg. dq d g q dq dq wr wr wr address macrocell outputs enable product term ( .oe ) ext cs ale read mux p d b cpld - input control reg. dir reg. input macrocell enable out data in output select output mux port pin data out address ai02885
psd4235g2 60/100 mcu i/o mode in the mcu i/o mode, the mcu uses the psd ports to expand its own i/o ports. by setting up the csiop space, the ports on the psd are mapped into the mcu address space. the addresses of the ports are listed in table 6. a port pin can be put into mcu i/o mode by writing a ?0? to the corresponding bit in the control regis- ter (for ports e, f and g). the mcu i/o direction may be changed by writing to the corresponding bit in the direction register, or by the output en- able product term. see the section entitled ?port operating modes?, on page 58. when the pin is configured as an output, the content of the data out register drives the pin. when configured as an input, the mcu can read the port input through the data in buffer. see figure 27. ports a, b and c do not have control registers, and are in mcu i/o mode by default. they can be used for pld i/o if they are specified in psdsoft express. pld i/o mode the pld i/o mode uses a port as an input to the cpld?s input macrocells (imc), and/or as an out- put from the cpld?s output macrocells (omc). the output can be tri-stated with a control signal. this output enable control signal can be defined by a product term from the pld, or by resetting the corresponding bit in the direction register to ?0?. the corresponding bit in the direction register must not be set to ?1? if the pin is defined for a pld input signal in psdsoft express. the pld i/o mode is specified in psdsoft express by declaring the port pins, and then specifying an equation in psdsoft express. address out mode for mcus with a multiplexed address/data bus, address out mode can be used to drive latched addresses onto the port pins. these port pins can, in turn, drive external devices. either the output enable or the corresponding bits of both the direc- tion register and control register must be set to a ?1? for pins to use address out mode. this must be done by the mcu at run-time. see table 41 for the address output pin assignments on ports e, f and g for various mcus. note: do not drive address signals with address out mode to an external memory device if it is in- tended for the mcu to boot from the external de- vice. the mcu must first boot from psd memory so the direction and control register bits can be set. table 39. port operating modes note: 1. can be multiplexed with other i/o functions. 2. available to motorola 16-bit 683xx and hc16 families of mcus. port mode port a port b port c port d port e port f port g m cu i/ o ye s ye s yes yes ye s yes yes pld i/o mcella outputs mcellb outputs additional ext. cs outputs pld inputs ye s no no ye s ye s ye s no ye s no no yes yes no no no yes no no no no no no yes yes no no no no address out no no no no yes (a7 - 0) yes (a7 - 0) yes (a7 - 0) or (a15 - 8) a ddres s in ye s ye s yes yes no yes no data port no no no no no yes yes peripheral i/o yes no no yes no yes no jtag isp no no no no yes 1 no no mcu reset mode 2 no no no no no yes yes
61/100 psd4235g2 table 40. port operating mode settings note: 1. n/a = not applicable 2. the direction of the port a,b,c, and f pins are controlled by the direction register ored with the individual output enable p roduct term (.oe) from the cpld and array. 3. any of these three methods enables the jtag pins on port e. 4. control register setting is not applicable to ports a, b and c. table 41. i/o port latched address output assignments note: 1. n/a = not applicable. mode defined in psdsoft express control register setting direction register setting vm register setting jtag enable mcu i/o declare pins only 0 (note 4 ) 1 = output, 0 = input (note 2 ) n/a n/a pld i/o declare pins and logic equations n/a (note 2 ) n/a n/a data port (port f, g) selected for mcu with non-multiplexed bus n/a n/a n/a n/a address out (port e, f, g) declare pins only 1 1 (note 2 ) n/a n/a address in (port a, b, c, d, f) declare pins or logic equation for input macrocells n/a n/a n/a n/a peripheral i/o (port f) logic equations (psel0 and psel1) n/a n/a pio bit = 1 n/a jtag isp 3 declare pins only n/a n/a n/a jtag_enable mcu reset mode specific pin logic level n/a n/a n/a n/a mcu port e (pe3-pe0) port e (pe7-pe4) port f (pf3-pf0) port f (pf7-pf4) port g (pg3-pg0) port g (pg7-pg4) 80c51xa n/a 1 address a7-a4 n/a address a7-a4 address a11-a8 address a15-a12 all other mcu with multiplexed bus address a3-a0 address a7-a4 address a3-a0 address a7-a4 address a11-a8 address a15-a12
psd4235g2 62/100 address in mode for mcus that have more than 16 address sig- nals, the higher addresses can be connected to port a, b, c, d or f, and are routed as inputs to the plds. the address input can be latched in the in- put macrocell (imc) by address strobe (ale/as, pd0). any input that is included in the dpld equa- tions for the primary flash memory, secondary flash memory or sram is considered to be an ad- dress input. data port mode ports f and g can be used as a data bus port for a mcu with a non-multiplexed address/data bus. the data port is connected to the data bus of the mcu. the general i/o functions are disabled in ports f and g if the ports are configured as a data port. data port mode is automatically configured in psdsoft express when a non-multiplexed bus mcu is selected. peripheral i/o mode peripheral i/o mode can be used to interface with external 8-bit peripherals. in this mode, all of port f serves as a tri-state, bi-directional data buffer for the mcu. peripheral i/o mode is enabled by set- ting bit 7 of the vm register to a '1.' figure 28 shows how port a acts as a bi-directional buffer for the mcu data bus if peripheral i/o mode is en- abled. an equation for psel0 and/or psel1 must be specified in psdsoft express. the buffer is tri- stated when psel0 or psel1 is not active. figure 28. peripheral i/o mode rd psel0 psel1 psel vm register bit 7 wr pa0 - pa7 d0 - d7 data bus ai02886
63/100 psd4235g2 jtag in-system programming (isp) port e is jtag compliant, and can be used for in- system programming (isp). you can multiplex jtag operations with other functions on port e because in-system programming (isp) is not per- formed during normal system operation. for more information on the jtag port, see the section en- titled ?reset (reset) timing?, on p age 75. mcu reset mode ports f and g can be configured to operate in mcu reset mode. this mode is available when psd is configured for the motorola 16-bit 683xx and hc16 family and is active only during reset. at the rising edge of the reset input, the mcu reads the logic level on the data bus (d15-d0) pins. the mcu then configures some of its i/o pin functions according to the logic level input on the data bus lines. two dedicated buffers are usually enabled during reset to drive the data bus lines to the desired logic level. the psd can replace the two buffers by configur- ing ports f and g to operate in mcu reset mode. in this mode, the psd will drive the pre-defined logic level or data pattern on to the mcu data bus when reset is active and there is no ongoing bus cycle. after reset, ports f and g return to the nor- mal data port mode. the mcu reset mode is enabled and configured in psdsoft express. the user defines the logic lev- el (data pattern) that will be drive out from ports f and g during reset. port configuration registers (pcr) each port has a set of port configuration regis- ters (pcr) used for configuration. the contents of the registers can be accessed by the mcu through normal read/write bus cycles at the addresses given in table 6. the addresses in table 6 are the offsets in hexadecimal from the base of the csiop register. the pins of a port are individually configurable and each bit in the register controls its respective pin. for example, bit 0 in a register refers to bit 0 of its port. the three port configuration registers (pcr), shown in table 42, are used for setting the port configurations. the default power-up state for each register in table 42 is 00h. control register any bit reset to ?0? in the control register sets the corresponding port pin to mcu i/o mode, and a ?1? sets it to address out mode. the default mode is mcu i/o. only ports e, f and g have an associat- ed control register. table 42. port configuration registers (pcr) note: 1. see table 46 for drive register bit definition. register name port mcu access control e, f, g write/read direction a, b, c, d, e, f, g write/read drive select 1 a, b, c, d, e, f, g write/read
psd4235g2 64/100 direction register the direction register controls the direction of data flow in the i/o ports. any bit set to ?1? in the direction register causes the corresponding pin to be an output, and any bit set to ?0? causes it to be an input. the default mode for all port pins is in- put. figure 29 and figure 31 show the port architec- ture diagrams for ports a/b/c and e/f/g, respec- tively. the direction of data flow for ports a, b, c and f are controlled not only by the direction reg- ister, but also by the output enable product term from the pld and array. if the output enable product term is not active, the direction register has sole control of a given pin?s direction. an example of a configuration for a port with the three least significant bits set to output and the re- mainder set to input is shown in table 45. since port d only contains four pins, the direction reg- ister for port d has only the four least significant bits active. drive select register. the drive select register configures the pin driver as open drain or cmos for some port pins, and controls the slew rate for the other port pins. an external pull-up resistor should be used for pins configured as open drain. a pin can be configured as open drain if its corre- sponding bit in the drive select register is set to a '1.' the default pin drive is cmos. (the slew rate is a measurement of the rise and fall times of an output. a higher slew rate means a faster output response and may create more elec- trical noise. a pin operates in a high slew rate when the corresponding bit in the drive register is set to '1.' the default rate is slow slew.) table 46 shows the drive register for ports a, b, c, d, e, f and g. it summarizes which pins can be configured as open drain outputs and which pins the slew rate can be set for. table 43. port pin direction control, output enable p.t. not defined table 44. port pin direction control, output enable p.t. defined table 45. port direction assignment example table 46. drive register pin assignment note: 1. na = not applicable. direction register bit port pin mode 0 input 1 output direction register bit output enable p. t. port pin mode 0 0 input 0 1 output 1 0 output 1 1 output bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 0 0 0 0 1 1 1 drive register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 port a open drain open drain open drain open drain open drain open drain open drain open drain port b open drain open drain open drain open drain open drain open drain open drain open drain port c slew rate slew rate slew rate slew rate slew rate slew rate slew rate slew rate port d na 1 na 1 na 1 na 1 open drain open drain open drain open drain port e open drain open drain open drain open drain open drain open drain open drain open drain port f slew rate slew rate slew rate slew rate slew rate slew rate slew rate slew rate port g open drain open drain open drain open drain open drain open drain open drain open drain
65/100 psd4235g2 port data registers the port data registers, shown in table 47, are used by the mcu to write data to or read data from the ports. table 47 shows the register name, the ports having each register type, and mcu access for each register type. the registers are described next. data in port pins are connected directly to the data in buff- er. in mcu i/o input mode, the pin input is read through the data in buffer. data out register stores output data written by the mcu in the mcu i/o output mode. the contents of the register are driven out to the pins if the direction register or the output enable product term is set to '1.' the contents of the register can also be read back by the mcu. output macrocells (omc) the cpld output macrocells (omc) occupy a lo- cation in the mcu?s address space. the mcu can read the output of the output macrocells (omc). if the mask macrocell register bits are not set, writ- ing to the macrocell loads data to the macrocell flip-flops. see the section entitled ?macrocell and i/ o port?, on page 41. mask macrocell register each mask macrocell register bit corresponds to an output macrocell (omc) flip-flop. when the mask macrocell register bit is set to a '1,' loading data into the output macrocell (omc) flip-flop is blocked. the default value is 0, or unblocked. input macrocells (imc) the input macrocells (imc) can be used to latch or store external inputs. the outputs of the input macrocells (imc) are routed to the pld input bus, and can be read by the mcu. see the section en- titled ?input macrocells (imc)?, on page 45. table 47. port data registers register name port mcu access data in a, b, c, d, e, f, g read - input on pin data out a, b, c, d, e, f, g write/read output macrocell a, b read - outputs of macrocells write - loading macrocells flip-flop mask macrocell a, b write/read - prevents loading into a given macrocell input macrocell a, b, c read - outputs of the input macrocells enable out a, b, c, f read - the output enable control of the port driver
psd4235g2 66/100 enable out the enable out register can be read by the mcu. it contains the output enable values for a given port. a '1' indicates the driver is in output mode. a '0' indicates the driver is in tri-state and the pin is in input mode. ports a, b and c - functionality and structure ports a, b and c have similar functionality and structure, as shown in figure 29. the ports can be configured to perform one or more of the following functions: mcu i/o mode cpld output - macrocells mcella7-mcella0 can be connected to port a. mcellb7-mcellb0 can be connected to port b. external chip select (ecs7-ecs0) can be connected to port c or port f. cpld input - via the input macrocells (imc). address in - additional high address inputs using the input macrocells (imc). open drain/slew rate - pins pc7-pc0 can be configured to fast slew rate. pins pa7-pa0 can be configured to open drain mode. figure 29. port a, b and c structure internal data bus data out register dq dq wr wr mcella7-mcella0 (port a) mcellb7-mcellb0 (port b) ext.cs (port c) enable product term ( .oe ) read mux p d b cpld - input dir register input macrocell enable out data in output mux port pin data out ai04936b
67/100 psd4235g2 port d - functionality and structure port d has four i/o pins. see figure 30. port d can be configured to perform one or more of the follow- ing functions: mcu i/o mode cpld input - direct input to the cpld, no input macrocells (imc) port d pins can be configured in psdsoft express as input pins for other dedicated functions: address strobe (ale/as, pd0) clkin (pd1) as input to the macrocells flip- flops and apd counter psd chip select input (csi , pd2). driving this signal high disables the flash memory, sram and csiop. write enable high-byte (wrh , pd3) input, or as dbe input from a mc68hc912. figure 30. port d structure internal data bus data out register dq dq wr wr read mux p d b cpld - input dir register data in output select output mux port d pin data out ai04937
psd4235g2 68/100 port e - functionality and structure port e can be configured to perform one or more of the following functions (see figure 31): mcu i/o mode in-system programming (isp) - jtag port can be enabled for programming/erase of the psd device. (see the section entitled ?reset (reset) timing?, on p age 75, for more information on jtag programming.) open drain - pins can be configured in open drain mode battery backup features ? pe6 can be configured for a battery input supply, voltage stand-by (v stby ). ? pe7 can be configured as a battery-on indicator (vbaton), indicating when v cc is less than v bat . latched address output - provide latched address output. port f - functionality and structure port f can be configured to perform one or more of the following functions: mcu i/o mode cpld output - external chip select (ecs7- ecs0) can be connected to port f or port c. cpld input - direct input to the cpld, no input macrocells (imc) latched address output - provide latched address output as per table 41. slew rate - pins can be configured for fast slew rate data port - connected to d7-d0 when port f is configured as data port for a non-multiplexed bus peripheral mode mcu reset mode - for 16-bit motorola 683xx and hc16 mcus port g - functionality and structure port g can be configured to perform one or more of the following functions: mcu i/o mode latched address output - provide latched address output as per table 41. open drain - pins can be configured in open drain mode data port - connected to d15-d8 when port g is configured as data port for a non- multiplexed bus mcu reset mode - for 16-bit motorola 683xx and hc16 mcus
69/100 psd4235g2 figure 31. port e, f and g structure internal data bus data out register dq d g q dq dq wr wr wr address ext. cs (port f) enable product term ( .oe ) ale read mux p d b cpld - input (port f) control register dir register enable out data in output select output mux port pin data out address a [ 7:0 ] or a [ 15:8 ] ai04938 isp or battery back-up (port e) configuration bit
psd4235g2 70/100 power management the psd device offers configurable power saving options. these options may be used individually or in combinations, as follows: ? all memory blocks in a psd (primary flash memory, secondary flash memory, and sram) are built with power management technology. in addition to using special silicon design methodology, power management technology puts the memories into standby mode when address/data inputs are not changing (zero dc current). as soon as a transition occurs on an input, the affected memory ?wakes up?, changes and latches its outputs, then goes back to standby. the designer does not have to do anything special to achieve memory stand-by mode when no inputs are changing?it happens automatically. the pld sections can also achieve stand-by mode when its inputs are not changing, as described for the power management mode registers (pmmr), later. ? the automatic power down (apd) block allows the psd to reduce to stand-by current automatically. the apd unit also blocks mcu address/data signals from reaching the memories and plds. this feature is available on all psd devices. the apd unit is described in more detail in the section entitled ?apd unit?, on page 71. built in logic monitors the address strobe of the mcu for activity. if there is no activity for a certain period (the mcu is asleep), the apd unit initiates power-down mode (if enabled). once in power-down mode, all address/data signals are blocked from reaching the psd memories and plds, and the memories are deselected internally. this allows the memories and plds to remain in stand-by mode even if the address/data signals are changing state externally (noise, other devices on the mcu bus, etc.). keep in mind that any unblocked pld input signals that are changing states keeps the pld out of stand- by mode, but not the memories. ? psd chip select input (csi , pd2) can be used to disable the internal memories, placing them in stand-by mode even if inputs are changing. this feature does not block any internal signals or disable the plds. this is a good alternative to using the apd unit, especially if your mcu has a chip select output. there is a slight penalty in memory access time when psd chip select input (csi , pd2) makes its initial transition from deselected to selected. ? the power management mode registers (pmmr) can be written by the mcu at run- time to manage power. all psd devices support ?blocking bits? in these registers that are set to block designated signals from reaching both plds. current consumption of the plds is directly related to the composite frequency of the changes on their inputs (see figure 35). significant power savings can be achieved by blocking signals that are not used in dpld or cpld logic equations at run-time. psdsoft express creates a fuse map that automatically blocks the low address byte (a7-a0) or the control signals (cntl0-cntl2, ale and write enable high-byte (wrh /dbe, pd3)) if none of these signals are used in pld logic equations. psd devices have a turbo bit in pmmr0. this bit can be set to turn the turbo mode off (the default is with turbo mode turned on). while turbo mode is off, the plds can achieve stand-by current when no pld inputs are changing (zero dc current). even when inputs do change, significant power can be saved at lower frequencies (ac current), compared to when turbo mode is on. when the turbo mode is on, there is a significant dc current component, and the ac component is higher.
71/100 psd4235g2 automatic power-down (apd) unit and power-down mode the apd unit, shown in figure 32, puts the psd into power-down mode by monitoring the activity of address strobe (ale/as, pd0). if the apd unit is enabled, as soon as activity on address strobe (ale/as, pd0) stops, a four-bit counter starts counting. if address strobe (ale/as, pd0) re- mains inactive for fifteen clock periods of clkin (pd1), power-down (pdn) goes high, and the psd enters power-down mode, as discussed next. power-down mode by default, if you enable the apd unit, power- down mode is automatically enabled. the device enters power-down mode if address strobe (ale/ as, pd0) remains inactive for fifteen periods of clkin (pd1). the following should be kept in mind when the psd is in power-down mode: ? if address strobe (ale/as, pd0) starts pulsing again, the psd returns to normal operation. the psd also returns to normal operation if either psd chip select input (csi , pd2) is low or the reset (reset ) input is high. ? the mcu address/data bus is blocked from all memory and plds. ? various signals can be blocked (prior to power-down mode) from entering the plds by setting the appropriate bits in the power management mode registers (pmmr). the blocked signals include mcu control signals and the common clkin (pd1). note that blocking clkin (pd1) from the plds does not block clkin (pd1) from the apd unit. ? all psd memories enter stand-by mode and are drawing stand-by current. however, the plds and i/o ports blocks do not go into stand-by mode because you do not want to have to wait for the logic and i/o to ?wake-up? before their outputs can change. see table 48 for power-down mode effects on psd ports. ? typical stand-by current is or the order of a. this stand-by current value assumes that there are no transitions on any pld input. table 48. effect of power-down mode on ports figure 32. apd unit table 49. psd timing and stand-by current during power-down mode note: 1. power-down does not affect the operation of the pld. the pld operation in this mode is based only on the turbo bit. 2. typical current consumption, see table 61, assuming no pld inputs are changing state and the pld turbo bit is 0. port function pin level mcu i/o no change pld out no change address out undefined data port tri-state peripheral i/o tri-state mode pld propagation delay memory access time access recovery time to normal access typical stand-by current power-down normal t pd (note 1 ) no access t lvdv i sb (note 2 ) apd en pmmr0 bit 1=1 ale reset csi clkin transition detection edge detect apd counter power down (pdn) select disable bus interface secondary flash memory select primary flash memory select sram select pd clr pd disable primary and secondary flash memory and sram pld ai04939
psd4235g2 72/100 other power saving options the psd offers other reduced power saving op- tions that are independent of the power-down mode. except for the sram stand-by and psd chip select input (csi , pd2) features, they are en- abled by setting bits in pmmr0 and pmmr2 (as summarised in table 23 and table 24). pld power management the power and speed of the plds are controlled by the turbo bit (bit 3) in pmmr0. by setting the bit to '1,' the turbo mode is off and the plds con- sume the specified stand-by current when the in- puts are not switching for an extended time of 70 ns. the propagation delay time is increased af- ter the turbo bit is set to ?1? (turned off) when the inputs change at a composite frequency of less than 15 mhz. when the turbo bit is reset to ?0? (turned on), the plds run at full power and speed. the turbo bit affects the pld?s dc power, ac power, and propagation delay. see the ac and dc characteristics tables for pld timing values (table 69). blocking mcu control signals with the pmmr2 bits can further reduce pld ac power consump- tion. sram stand-by mode (battery backup) the psd supports a battery backup mode in which the contents of the sram are retained in the event of a power loss. the sram has voltage stand-by (v stby , pe6) that can be connected to an external battery. when v cc becomes lower than v stby then the psd automatically connects to voltage stand-by (v stby , pe6) as a power source to the sram. the sram stand-by current (i stby ) is typ- ically 0.5a. the sram data retention voltage is 2 v minimum. the battery-on indicator (vbaton) can be routed to pe7. this signal indicates when the v cc has dropped below v stby , and that the sram is running on battery power. psd chip select input (csi , pd2) pd2 of port d can be configured in psdsoft ex- press as psd chip select input (csi ). when low, the signal selects and enables the internal primary flash memory, secondary flash memory, sram, and i/o blocks for read or write operations in- volving the psd. a high on psd chip select input (csi , pd2) disables the primary flash memory, secondary flash memory, and sram, and reduc- es the psd power consumption. however, the pld and i/o signals remain operational when psd chip select input (csi , pd2) is high. there may be a timing penalty when using psd chip select input (csi , pd2) depending on the speed grade of the psd that you are using. see the timing parameter t slqv in table 69. input clock the psd provides the option to turn off clkin (pd1) to the pld to save ac power consumption. clkin (pd1) is an input to the pld and array and the output macrocells (omc). during power-down mode, or, if clkin (pd1) is not being used as part of the pld logic equation, the clock should be disabled to save ac power. clkin (pd1) is disconnected from the pld and array or the macrocells block by setting bits 4 or 5 to a ?1? in pmmr0. figure 33. enable power-down flow chart enable apd set pmmr0 bit 1 = 1 psd in power down mode ale/as idle for 15 clkin clocks? reset yes no optional disable desired inputs to pld by setting pmmr0 bits 4 and 5 and pmmr2 bits 0 to 6. ai04940
73/100 psd4235g2 input control signals the psd provides the option to turn off the ad- dress input (a7-a0) and input control signals (cntl0, cntl1, cntl2, address strobe (ale/ as, pd0) and write enable high-byte (wrh /dbe, pd3)) to the pld to save ac power consumption. these signals are inputs to the pld and array. during power-down mode, or, if any of them are not being used as part of the pld logic equation, these control signals should be disabled to save ac power. they are disconnected from the pld and array by setting bits 0, 2, 3, 4, 5 and 6 to a ?1? in pmmr2. table 50. apd counter operation apd enable bit ale pd polarity ale level apd counter 0 x x not counting 1 x pulsing not counting 1 1 1 counting (generates pdn after 15 clocks) 1 0 0 counting (generates pdn after 15 clocks)
psd4235g2 74/100 power-on reset, warm reset and power-down power-on reset upon power-up, the psd requires a reset (re- set ) pulse of duration t nlnh-po (minimum 1 ms) after v cc is steady. during this period, the device loads internal configurations, clears some of the registers and sets the flash memory into operat- ing mode. after the rising edge of reset (reset ), the psd remains in the reset mode for an addi- tional period, t opr (maximum 120 ns), before the first memory access is allowed. the psd flash memory is reset to the read mode upon power-up. sector select (fs0-fs7 and csboot0-csboot3) must all be low, write strobe (wr /wrl , cntl0) high, during power on reset for maximum security of the data contents and to remove the possibility of data being written on the first edge of write strobe (wr /wrl , cntl0). any flash memory write cycle initiation is prevented automatically when v cc is below v l- ko . warm reset once the device is up and running, the device can be reset with a pulse of a much shorter duration, t nlnh (minimum 150 ns). the same t opr period is needed before the device is operational after warm reset. figure 34 shows the timing of the power-up and warm reset. i/o pin, register and pld status at reset table 51 shows the i/o pin, register and pld sta- tus during power on reset, warm reset and pow- er-down mode. pld outputs are always valid during warm reset, and they are valid in power on reset once the internal psd configuration bits are loaded. this loading of psd is completed typically long before the v cc ramps up to operating level. once the pld is active, the state of the outputs are determined by equations specified in psdsoft ex- press. reset of flash memory erase and program cycles an external reset (reset ) also resets the inter- nal flash memory state machine. during a flash memory program or erase cycle, reset (reset ) terminates the cycle and returns the flash memo- ry to the read mode within a period of t nlnh-a (minimum 25 s). table 51. status during power-on reset, warm reset and power-down mode note: 1. the sr_code and peripheral mode bits in the vm register are always cleared to ?0? on power-on reset or warm reset. port configuration power-on reset warm reset power-down mode mcu i/o input mode input mode unchanged pld output valid after internal psd configuration bits are loaded valid depends on inputs to pld (addresses are blocked in pd mode) address out tri-stated tri-stated not defined data port tri-stated tri-stated tri-stated peripheral i/o tri-stated tri-stated tri-stated register power-on reset warm reset power-down mode pmmr0 and pmmr2 cleared to ?0? unchanged unchanged macrocells flip-flop status cleared to ?0? by internal power-on reset depends on .re and .pr equations depends on .re and .pr equations vm register 1 initialized, based on the selection in psdsoft express configuration menu initialized, based on the selection in psdsoft express configuration menu unchanged all other registers cleared to ?0? cleared to ?0? unchanged
75/100 psd4235g2 figure 34. reset (reset ) timing programming in-circuit using the jtag serial interface the jtag serial interface on the psd can be en- abled on port e (see table 52). all memory blocks (primary flash memory and secondary flash memory), pld logic, and psd configuration bits may be programmed through the jtag-isc serial interface. a blank device can be mounted on a printed circuit board and programmed using jtag in-system programming (isp). the standard jtag signals (i eee 1149.1) are tms, tck, tdi, and tdo. two additional signals, tstat and terr , are optional jtag extensions used to speed up prog ram and erase cycles. by default, on a blank psd (as shipped from the factory, or after erasure), four pins on port e are enabled for the basic jtag signals tms, tck, tdi, and tdo . see application note an1153 for more details on jtag in-system programming (isp). standard jtag signals the standard jtag signals (tms, tck, tdi, and tdo) can be enabled by any of three different con- ditions that are logically ored. when enabled, tdi, tdo, tck, and tms are inputs, waiting for a serial command from an external jtag controller device (such as flashlink or automated test equipment). when the enabling command is re- ceived from the external jtag controller device, tdo becomes an output and the jtag channel is fully functional inside the psd. the same com- mand that enables the jtag channel may option- ally enable the two additional jtag pins, tstat and terr . the following symbolic logic equation specifies the conditions enabling the four basic jtag pins (tms, tck, tdi, and tdo) on their respective port e pins. for purposes of discussion, the logic label jtag_on is used. when jtag_on is true, the four pins are enabled for jtag. when jtag_on is false, the four pins can be used for general psd i/o. jtag_on = psdsoft express_enabled + /* an nvm configuration bit inside the psd is set by the designer in the psdsoft express configuration utility. this dedicates the pins for jtag at all times (compliant with ieee 1149.1 */ microcontroller_enabled + /* the microcontroller can set a bit at run-time by writing to the psd register, jtag enable. this register is located at address csiop + offset c7h. setting the jtag_enable bit in this register will enable the pins for jtag use. this bit is cleared by a psd reset or the microcontroller. see table 21 for bit definition. */ psd_product_term_enabled; /* a dedicated product term (pt) inside the psd can be used to enable the jtag pins. this pt has the reserved name jtagsel. once defined as a node in psdabel, the designer can write an equation for jtagsel. this method is used when the port e jtag pins are multiplexed with other i/o signals. it is recommended to tie logically the node jtagsel to the jen\ signal on the flashlink cable when multiplexing jtag signals. see application note 1153 for details. */ t nlnh-po t opr ai02866b reset t nlnh t nlnh-a t opr v cc v cc (min) power-on reset warm reset
psd4235g2 76/100 the state of the psd reset (reset ) signal does not interrupt (or prevent) jtag operations if the jtag pins are dedicated by an nvm configuration bit (via psdsoft express). however, reset (re- set ) will prevent or interrupt jtag operations if the jtag enable register (as shown in table 21) is used to enable the jtag pins. the psd supports jtag in-system-programma- bility (isp) commands, but not boundary scan. st?s psdsoft express software tool and flashlink jtag programming cable implement the jtag in-system-programmability (isp) com- mands. jtag extensions tstat and terr are two jtag extension signals enabled by a jtag command received over the four standard jtag pins (tms, tck, tdi, and tdo). they are used to speed program and erase cycles by indicating status on psd pins instead of having to scan the status out serially using the standard jtag channel. see application note an1153 . terr indicates if an error has occurred when erasing a sector or programming in flash memory. this signal goes low (active) when an error con- dition occurs, and stays low until a specific jtag command is executed or a reset (reset ) pulse is received after an ?isc_disable? command. tstat behaves the same as ready/busy (pe4) described in the section entitled ?ready/busy (pe4)?, on page 26. tstat is high when the psd4235g2 device is in read mode (primary flash memory and secondary flash memory con- tents can be read). tstat is low when flash memory program or erase cycles are in progress, and also when data is being written to the second- ary flash memory . tstat and terr can be configured as open- drain type signals with a jtag command. note: the state of reset (reset ) does not inter- rupt (or prevent) jtag operations if the jtag sig- nals are dedicated by an nvm configuration bit (via psdsoft express). however, reset (reset ) prevents or interrupts jtag operations if the jtag enable register (as shown in table 21) is used to enable the jtag signals. security and flash memory protection when the security bit is set, the device cannot be read on a device programmer or through the jtag port. when using the jtag port, only a full chip erase command is allowed. all other program, erase and verify commands are blocked. full chip erase returns the device to a non-secured blank state. the security bit can be set in psdsoft express. all primary flash memory and secondary flash memory sectors can individually be sector protect- ed against erasure. the sector protect bits can be set in psdsoft express. table 52. jtag port signals initial delivery state when delivered from st, the psd device has all bits in the memory and plds set to '1.' the psd configuration register bits are set to '0.' the code, configuration, and pld logic are loaded using the programming procedure. information for program- ming the device is available directly from st. please contact your local sales representative. port e pin jtag signals description pe0 tms mode select pe1 tck clock pe2 tdi serial data in pe3 tdo serial data out pe4 tstat status pe5 terr error flag
77/100 psd4235g2 ac/dc parameters these tables describe the ad and dc parameters of the psd4235g2: dc electrical specification ac timing specification pld timing ? combinatorial timing ? synchronous clock mode ? asynchronous clock mode ? input macrocell timing mcu timing ? read timing ?write timing ? peripheral mode timing ? power-down and reset timing the following are issues concerning the parame- ters presented: in the dc specification the supply current is given for different modes of operation. before calculating the total power consumption, determine the percentage of time that the psd is in each mode. also, the supply power is considerably different if the turbo bit is 0. the ac power component gives the pld, flash memory, and sram ma/mhz specification. figure 35 show the pld ma/ mhz as a function of the number of product terms (pt) used. in the pld timing parameters, add the required delay when turbo bit is 0. figure 35. pld i cc /frequency consumption ai05739 0 10 20 30 40 50 60 70 80 90 100 110 0 5 10 15 20 25 highest composite frequency at pld inputs (mhz) icc - (ma) pt 100% pt 25% vcc = 5v turbo on (100%) turbo on (25%) turbo off turbo off
psd4235g2 78/100 table 53. example of psd typical power calculation at v cc = 5.0v (with turbo mode on) conditions highest composite pld input frequency (freq pld) = 8 mhz mcu ale frequency (freq ale) = 4 mhz % flash memory access = 80% % sram access = 15% % i/o access = 5% (no additional power above base) operational modes % normal = 10% % power-down mode = 90% number of product terms used (from fitter report) = 45 pt % of total product terms = 45/193 = 23.3% turbo mode = on calculation (using typical values) i cc total = ipwrdown x %pwrdown + %normal x (i cc (ac) + i cc (dc)) = ipwrdown x %pwrdown + % normal x (%flash x 2.5 ma/mhz x freq ale + %sram x 1.5 ma/mhz x freq ale + % pld x 2 ma/mhz x freq pld + #pt x 400a/pt) = 50a x 0.90 + 0.1 x (0.8 x 2.5 ma/mhz x 4 mhz + 0.15 x 1.5 ma/mhz x 4 mhz + 2 ma/mhz x 8 mhz + 45 x 0.4 ma/pt) = 45a + 0.1 x (8 + 0.9 + 16 + 18 ma) = 45a + 0.1 x 42.9 = 45a + 4.29 ma = 4.34 ma this is the operating power with no flash memory program or erase cycles in progress. calculation is based on i out = 0 ma.
79/100 psd4235g2 table 54. example of psd typical power calculation at v cc = 5.0v (with turbo mode off) conditions highest composite pld input frequency (freq pld) = 8 mhz mcu ale frequency (freq ale) = 4 mhz % flash memory access = 80% % sram access = 15% % i/o access = 5% (no additional power above base) operational modes % normal = 10% % power-down mode = 90% number of product terms used (from fitter report) = 45 pt % of total product terms = 45/193 = 23.3% turbo mode = off calculation (using typical values) i cc total = ipwrdown x %pwrdown + %normal x (i cc (ac) + i cc (dc)) = ipwrdown x %pwrdown + % normal x (%flash x 2.5 ma/mhz x freq ale + %sram x 1.5 ma/mhz x freq ale + % pld x (from graph using freq pld)) = 50a x 0.90 + 0.1 x (0.8 x 2.5 ma/mhz x 4 mhz + 0.15 x 1.5 ma/mhz x 4 mhz + 24 ma) = 45a + 0.1 x (8 + 0.9 + 24) = 45a + 0.1 x 32.9 = 45a + 3.29 ma = 3.34 ma this is the operating power with no flash memory program or erase cycles in progress. calculation is based on i out = 0 ma.
psd4235g2 80/100 maximum rating stressing the device above the rating listed in the absolute maximum ratings" table may cause per- manent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not im- plied. exposure to absolute maximum rating con- ditions for extended periods may affect device reliability. refer also to the stmicroelectronics sure program and other relevant quality docu- ments. table 55. absolute maximum ratings note: 1. ipc/jedec j-std-020a 2. jedec std jesd22-a114a (c1=100 pf, r1=1500 ? , r2=500 ? ) symbol parameter min. max. unit t stg storage temperature ?65 125 c t lead lead temperature during soldering (20 seconds max.) 1 235 c v io input and output voltage (q = v oh or hi-z) ?0.6 7.0 v v cc supply voltage ?0.6 7.0 v v pp device programmer supply voltage ?0.6 14.0 v v esd electrostatic discharge voltage (human body model) 2 ?2000 2000 v
81/100 psd4235g2 dc and ac parameters this section summarizes the operating and mea- surement conditions, and the dc and ac charac- teristics of the device. the parameters in the dc and ac characteristic tables that follow are de- rived from tests performed under the measure- ment conditions summarized in the relevant tables. designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parame- ters. table 56. operating conditions table 57. ac signal letters for pld timings note: example: t avlx = time from address valid to ale invalid. table 58. ac signal behavior symbols for pld timings note: example: t avlx = time from address valid to ale invalid. table 59. ac measurement conditions note: 1. output hi-z is defined as the point where data out is no longer driven. symbol parameter min. max. unit v cc supply voltage 4.5 5.5 v t a ambient operating temperature (industrial) ?40 85 c ambient operating temperature (commercial) 0 70 c a address input c ceout output d input data e e input g internal wdog_on signal i interrupt input l ale input n reset input or output p port signal output qoutput data rwr , uds , lds , ds , iord, psen inputs s chip select input tr/w input w internal pdn signal b v stby output m output macrocell ttime l logic level low or ale h logic level high v valid x no longer a valid logic level zfloat pw pulse width symbol parameter min. max. unit c l load capacitance 30 pf
psd4235g2 82/100 table 60. capacitance note: 1. sampled only, not 100% tested. 2. typical values are for t a = 25c and nominal supply voltages. figure 36. ac measurement i/o waveform figure 37. ac measurement load circuit figure 38. switching waveforms - key symbol parameter test condition typ . 2 max. unit c in input capacitance (for input pins) v in = 0v 46 pf c out output capacitance (for input/ output pins) v out = 0v 812 pf c vpp capacitance (for cntl2/v pp )v pp = 0v 18 25 pf 3.0v 0v test point 1.5v ai03103b device under test 2.01 v 195 ? c l = 30 pf (including scope and jig capacitance) ai03104b waveforms inputs outputs steady input may change from hi to lo may change from lo to hi don't care outputs only steady output will be changing from hi to lo will be changing lo to hi changing, state unknown center line is tri-state ai03102
83/100 psd4235g2 table 61. dc characteristics note: 1. reset (reset ) has hysteresis. v il1 is valid at or below 0.2v cc ?0.1. v ih1 is valid at or above 0.8v cc . 2. csi deselected or internal power-down mode is active. 3. pld is in non-turbo mode, and none of the inputs are switching. 4. please see figure 35 for the pld current calculation. symbol parameter test condition (in addition to those in table 56) min. typ. max. unit v ih input high voltage 4.5v < v cc < 5.5v 2 v cc +0.5 v v il input low voltage 4.5v < v cc < 5.5v ?0.5 0.8 v v ih1 reset high level input voltage (note 1 ) 0.8v cc v cc +0.5 v v il1 reset low level input voltage (note 1 ) ?0.5 0.2v cc ?0.1 v v hys reset pin hysteresis 0.3 v v lko v cc (min) for flash erase and program 2.5 4.2 v v ol output low voltage i ol = 20a, v cc = 4.5v 0.01 0.1 v i ol = 8 ma, v cc = 4.5v 0.25 0.45 v v oh output high voltage except v stby on i oh = ?20a, v cc = 4.5v 4.4 4.49 v i oh = ?2 ma, v cc = 4.5v 2.4 3.9 v v oh1 output high voltage v stby on i oh1 = 1a v stby ? 0.8 v v stby sram stand-by voltage 2.0 v cc v i stby sram stand-by current v cc = 0v 0.5 1 a i idle idle current (v stby input) v cc > v stby ?0.1 0.1 a v df sram data retention voltage only on v stby 2v i sb stand-by supply current for power-down mode csi >v cc ?0.3v (notes 2,3 ) 100 200 a i li input leakage current v ss < v in < v cc ?1 0.1 1 a i lo output leakage current 0.45 < v out < v cc ?10 5 10 a i cc (dc) (note 5 ) operating supply current pld only pld_turbo = off, f = 0 mhz (note 5 ) 0 a/pt pld_turbo = on, f = 0 mhz 400 700 a/pt flash memory during flash memory write/erase only 15 30 ma read only, f = 0 mhz 0 0 ma sram f = 0 mhz 0 0 ma i cc (ac) (note 5 ) pld ac adder note 4 flash memory ac adder 2.5 3.5 ma/ mhz sram ac adder 1.5 3.0 ma/ mhz
psd4235g2 84/100 figure 39. input to output disable / enable table 62. cpld combinatorial timing note: 1. fast slew rate output available on port c and port f. table 63. cpld macrocell synchronous clock mode timing note: 1. fast slew rate output available on port c and port f. 2. clkin (pd1) t clcl = t ch + t cl . symbol parameter conditions -70 -90 fast pt aloc turbo off slew rate 1 unit min max min max t pd cpld input pin/ feedback to cpld combinatorial output 20 25 + 2 + 12 ? 2 ns t ea cpld input to cpld output enable 21 26 + 12 ? 2 ns t er cpld input to cpld output disable 21 26 + 12 ? 2 ns t arp cpld register clear or preset delay 21 26 + 12 ? 2 ns t arpw cpld register clear or preset pulse width 10 20 + 12 ns t ard cpld array delay any macrocell 11 16 + 2 ns symbol parameter conditions -70 -90 fast pt aloc turbo off slew rate 1 unit min max min max f max maximum frequency external feedback 1/(t s +t co ) 34.4 30.30 mhz maximum frequency internal feedback (f cnt ) 1/(t s +t co ?10) 52.6 43.48 mhz maximum frequency pipelined data 1/(t ch +t cl ) 83.3 50.00 mhz t s input setup time 14 15 + 2 + 12 ns t h input hold time 0 0 ns t ch clock high time clock input 6 10 ns t cl clock low time clock input 6 10 ns t co clock to output delay clock input 15 18 ? 2 ns t ard cpld array delay any macrocell 11 16 + 2 ns t min minimum clock period 2 t ch +t cl 12 20 ns ter tea input input to output enable/disable ai02863
85/100 psd4235g2 table 64. cpld macrocell asynchronous clock mode timing figure 40. synchronous clock mode timing - pld symbol parameter conditions -70 -90 pt aloc turbo off slew rate unit min max min max f maxa maximum frequency external feedback 1/(t sa +t coa ) 38.4 26.32 mhz maximum frequency internal feedback (f cnta ) 1/(t sa +t coa ?10) 62.5 35.71 mhz maximum frequency pipelined data 1/(t cha +t cla ) 47.6 37.03 mhz t sa input setup time 6 8 + 2 + 12 ns t ha input hold time 7 12 ns t cha clock input high time 9 12 + 12 ns t cla clock input low time 12 15 + 12 ns t coa clock to output delay 21 30 + 12 ? 2 ns t arda cpld array delay any macrocell 11 16 + 2 ns t mina minimum clock period 1/f cnta 16 28 ns t ch t cl t co t h t s clkin input registered output ai02860
psd4235g2 86/100 figure 41. asynchronous reset / preset figure 42. asynchronous clock mode timing (product term clock) figure 43. input macrocell timing (product term clock) table 65. input macrocell timing note: 1. inputs from port a, b, and c relative to register/latch clock from the pld. ale latch timings refer to t avlx and t lxax . symbol parameter conditions -70 -90 pt aloc turbo off unit min max min max t is input setup time (note 1 ) 00 ns t ih input hold time (note 1 ) 15 20 + 12 ns t inh nib input high time (note 1 ) 912 ns t inl nib input low time (note 1 ) 912 ns t ino nib input to combinatorial delay (note 1 ) 34 46 + 2 + 12 ns tarp register output tarpw reset/preset input ai02864 tcha tcla tcoa tha tsa clock input registered output ai02859 t inh t inl t ino t ih t is pt clock input output ai03101
87/100 psd4235g2 table 66. program, write and erase times note: 1. programmed to all zero before erase. 2. the polling status, dq7, is valid tq7vqv time units before the data byte, dq0-dq7, is valid for reading. 3. dq7 is dq15 for motorola mcu with 16-bit data bus. figure 44. peripheral i/o write timing symbol parameter min. typ. max. unit flash program 8.5 s flash bulk erase 1 (pre-programmed) 330s flash bulk erase (not pre-programmed) 10 s t whqv3 sector erase (pre-programmed) 1 30 s t whqv2 sector erase (not pre-programmed) 2.2 s t whqv1 byte program 14 1200 s program / erase cycles (per sector) 100,000 cycles t whwlo sector erase time-out 100 s t q7vqv dq7 valid to output (dq7-dq0) valid (data polling) 2 30 ns tdvqv (pf) twlqv (pf) twhqz (pf) address data out a /d bus wr port f data out ale /as ai05741
psd4235g2 88/100 figure 45. read timing note: 1. t avlx and t lxax are not required for 80c251 in page mode or 80c51xa in burst mode. t avlx t lxax 1 t lvlx t avqv t slqv t rlqv t rhqx trhqz t eltl t ehel t rlrh t theh t avpv address valid address valid data valid data valid address out ale /as a/d multiplexed bus address non-multiplexed bus data non-multiplexed bus csi rd (psen, ds) e r/w ai02895
89/100 psd4235g2 table 67. read timing note: 1. rd timing has the same timing as ds , lds , uds , and psen signals. 2. rd and psen have the same timing. 3. any input used to select an internal psd function. 4. in multiplexed mode, latched addresses generated from adio delay to address output on any port. 5. rd timing has the same timing as ds , lds , and uds signals. symbol parameter conditions -70 -90 turbo off unit min max min max t lvlx ale or as pulse width 15 20 ns t avlx address setup time (note 3 ) 46 ns t lxax address hold time (note 3 ) 78 ns t avqv address valid to data valid (note 3 ) 70 90 + 12 ns t slqv cs valid to data valid 75 100 ns t rlqv rd to data valid 8-bit bus (note 5 ) 24 32 ns rd or psen to data valid 8-bit bus, 8031, 80251 (note 2 ) 31 38 ns t rhqx rd data hold time (note 1 ) 00 ns t rlrh rd pulse width (note 1 ) 27 32 ns t rhqz rd to data high-z (note 1 ) 20 25 ns t ehel e pulse width 27 32 ns t theh r/w setup time to enable 6 10 ns t eltl r/w hold time after enable 0 0 ns t avpv address input valid to address output delay (note 4 ) 20 25 ns
psd4235g2 90/100 figure 46. write timing t avlx t lxax t lvlx t avwl t slwl t whdx t whax t eltl t ehel t wlmv t wlwh t dv wh t theh t avpv address valid address valid data valid data valid address out t whpv standard mcu i/o out ale / as a/d multiplexed bus address non-multiplexed bus data non-multiplexed bus csi wr (ds) e r/ w ai02896
91/100 psd4235g2 table 68. write timing note: 1. any input used to select an internal psd function. 2. in multiplexed mode, latched address generated from adio delay to address output on any port. 3. wr has the same timing as e, ds , lds , uds , wrl , and wrh signals. 4. assuming data is stable before active write signal. 5. assuming write is active before data becomes valid. 6. twhax2 is the address hold time for dpld inputs that are used to generate sector select signals for internal psd memory. 7. twhax is 6 ns when writing to the output macrocell registers ab and bc. symbol parameter conditions -70 -90 unit min max min max t lvlx ale or as pulse width 15 20 ns t avlx address setup time (note 1 ) 46ns t lxax address hold time (note 1 ) 78ns t avwl address valid to leading edge of wr (notes 1,3 ) 815ns t slwl cs valid to leading edge of wr (note 3 ) 12 15 ns t dvwh wr data setup time (note 3 ) 25 35 ns t whdx wr data hold time (note 3,7 ) 45ns t wlwh wr pulse width (note 3 ) 28 35 ns t whax1 trailing edge of wr to address invalid (note 3 ) 68ns t whax2 trailing edge of wr to dpld address invalid (note 3,6 ) 00ns t whpv trailing edge of wr to port output valid using i/o port data register (note 3 ) 27 30 ns t dvmv data valid to port output valid using macrocell register preset/clear (notes 3,5 ) 42 55 ns t avpv address input valid to address output delay (note 2 ) 20 25 ns t wlmv wr valid to port output valid using macrocell register preset/clear (notes 3,4 ) 48 55 ns
psd4235g2 92/100 figure 47. peripheral i/o read timing table 69. port f peripheral data mode read timing table 70. port f peripheral data mode write timing note: 1. rd has the same timing as ds , lds , uds , and psen (in 8031 combined mode). 2. wr has the same timing as the e, lds , uds , wrl , and wrh signals. 3. any input used to select port f data peripheral mode. 4. data is already stable on port f. 5. data stable on adio pins to data on port f. symbol parameter conditions -70 -90 turbo off unit min max min max t avqv?pf address valid to data valid (note 3 ) 30 35 + 12 ns t slqv?pf csi valid to data valid 25 35 + 12 ns t rlqv?pf rd to data valid (notes 1,4 ) 21 32 ns rd to data valid 8031 mode 31 38 ns t dvqv?pf data in to data out valid 22 30 ns t qxrh?pf rd data hold time 0 0 ns t rlrh?pf rd pulse width (note 1 ) 27 32 ns t rhqz?pf rd to data high-z (note 1 ) 23 25 ns symbol parameter conditions -70 -90 unit min max min max t wlqv?pf wr to data propagation delay (note 2 ) 25 35 ns t dvqv?pf data to port f data propagation delay (note 5 ) 22 30 ns t whqz?pf wr invalid to port f tri-state (note 2 ) 20 25 ns t qxrh ( pf) t rlqv ( pf) t rlrh ( pf) t dvqv ( pf) t rhqz ( pf) t slqv ( pf) t avqv ( pf) address data valid ale /as a /d bus rd data on port f csi ai05740
93/100 psd4235g2 figure 48. reset (reset ) timing table 71. reset (r eset )timing note: 1. reset (reset ) does not reset flash memory program or erase cycles. 2. warm reset aborts flash memory program or erase cycles, and puts the device in read mode. table 72. power-down timing note: 1. t clcl is the period of clkin (pd1). table 73. v stbyon timing note: 1. v stbyon timing is measured at v cc ramp rate of 2 ms. symbol parameter conditions min max unit t nlnh reset active low time 1 150 ns t nlnh?po power on reset active low time 1 ms t nlnh?a warm reset 2 25 s t opr reset high to operational device 120 ns symbol parameter conditions -70 -90 unit min max min max t lvdv ale access time from power-down 80 90 ns t clwh maximum delay from apd enable to internal pdn valid signal using clkin (pd1) 15 * t clcl 1 s symbol parameter conditions min typ max unit t bvbh v stby detection to v stbyon output high (note 1 ) 20 s t bxbl v stby off detection to v stbyon output low (note 1 ) 20 s t nlnh-po t opr ai02866b reset t nlnh t nlnh-a t opr v cc v cc (min) power-on reset warm reset
psd4235g2 94/100 figure 49. isc timing table 74. isc timing note: 1. for non-pld programming, erase or in isc by-pass mode. 2. for program or erase pld only. symbol parameter conditions -70 -90 unit min max min max t isccf clock (tck, pc1) frequency (except for pld) (note 1 ) 20 18 mhz t iscch clock (tck, pc1) high time (except for pld) (note 1 ) 23 26 ns t isccl clock (tck, pc1) low time (except for pld) (note 1 ) 23 26 ns t isccfp clock (tck, pc1) frequency (pld only) (note 2 ) 22mhz t iscchp clock (tck, pc1) high time (pld only) (note 2 ) 240 240 ns t iscclp clock (tck, pc1) low time (pld only) (note 2 ) 240 240 ns t iscpsu isc port set up time 6 8 ns t iscph isc port hold up time 5 5 ns t iscpco isc port clock to output 21 23 ns t iscpzv isc port high-impedance to valid output 21 23 ns t iscpvz isc port valid output to high-impedance 21 23 ns iscch tck tdi/tms isc outputs/tdo isc outputs/tdo t isccl t iscph t iscpsu t iscpvz t iscpzv t iscpco t ai02865
95/100 psd4235g2 package mechanical figure 50. tqfp80 - 80-lead plastic thin, quad, flat package outline note: drawing is not to scale. qfp-a nd e1 cp b e a2 a n l a1 d1 d 1 e ne c d2 e2 l1
psd4235g2 96/100 table 75. tqfp80 - 80-lead plastic thin, quad, flat package mechanical data symb mm inches typ min max typ min max a ? ?1.60? ?0.063 a1 ? 0.05 0.15 ? 0.002 0.006 a2 1.40 1.35 1.45 0.055 0.053 0.057 b 0.22 0.17 0.27 0.009 0.007 0.011 c ? 0.09 0.20 ? 0.004 0.008 d 14.00 ? ? 0.551 ? ? d1 12.00 ? ? 0.472 ? ? d2 9.50 ? ? 0.374 ? ? e 14.00 ? ? 0.551 ? ? e1 12.00 ? ? 0.472 ? ? e2 9.50 ? ? 0.374 ? ? e0.50? ?0.020? ? l 0.60 0.45 0.75 0.024 0.018 0.030 l1 1.00 ? ? 0.039 ? ? 3.5 0 7 3.5 0 7 n80 80 nd 20 20 ne 20 20 cp ? ? 0.08 ? ? 0.003
97/100 psd4235g2 part numbering table 76. ordering information scheme note: 1. the 3.3v10% devices are not covered by this data sheet, but by the psd4235g2v data sheet. for a list of available options (e.g., speed, package) or for further information on any aspect of this device, please contact the st sales office nearest to you. example: psd42 3 5 g 2 ? 90 u 1 t device type psd42 = flash psd with cpld sram size 3 = 64 kbit flash memory size 5 = 4 mbit i/o count g = 52 i/o 2nd non-volatile memory 2 = 256 kbit flash memory operating voltage blank = v cc = 4.5 to 5.5v v (1) = v cc = 3.0 to 3.6v speed 70 = 70ns 90 = 90ns 12 = 120ns package u = tqfp80 temperature range blank = 0 to 70c (commercial) i = ?40 to 85c (industrial) option t = tape & reel packing
psd4235g2 98/100 appendix a. pin assignments table 77. psd4235g2 tqfp80 pin no. pin assignments pin no. pin assignments pin no. pin assignments pin no. pin assignments 1 pd2 21 pg0 41 pc0 61 pb0 2 pd3 22 pg1 42 pc1 62 pb1 3 ad0 23 pg2 43 pc2 63 pb2 4 ad1 24 pg3 44 pc3 64 pb3 5 ad2 25 pg4 45 pc4 65 pb4 6 ad3 26 pg5 46 pc5 66 pb5 7 ad4 27 pg6 47 pc6 67 pb6 8 gnd 28 pg7 48 pc7 68 pb7 9 v cc 29 v cc 49 gnd 69 v cc 10 ad5 30gnd 50gnd 70gnd 11 ad6 31 pf0 51 pa0 71 pe0 12 ad7 32 pf1 52 pa1 72 pe1 13 ad8 33 pf2 53 pa2 73 pe2 14 ad9 34 pf3 54 pa3 74 pe3 15 ad10 35 pf4 55 pa4 75 pe4 16 ad11 36 pf5 56 pa5 76 pe5 17 ad12 37 pf6 57 pa6 77 pe6 18 ad13 38 pf7 58 pa7 78 pe7 19 ad14 39 reset 59 cntl0 79 pd0 20 ad15 40 cntl2 60 cntl1 80 pd1
99/100 psd4235g2 revision history table 78. document revision history date rev. description of revision may 01, 2001 1.0 initial release as a wsi document 01-aug-01 1.1 timing parameters updated 12-sep-01 2.0 document rewritten using the st template 14-dec-01 2.1 information on the 3.3v10% range removed to a separate data sheet 11-mar-04 3.0 reformatted; corrected mechanical dimension, ordering (table 75, 76)
psd4235g2 100/100 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is g ranted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publication are subject to change wit hout notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectronics. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2004 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states www.st.com

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